CTNF 18/125,455 CTNF 90001 DETAILED ACTION Examiner’s Note Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims . Therefore elements, ‘second region’, ‘third region’, ‘fourth region’, ‘second direction’, ‘second source or drain region’, ‘first gate structure’, ‘second gate structure’, ‘second conductive structure, ‘third conductive structure, ‘fourth conductive structure ’ cited in claims 1, 8 and 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The applicant is being requested to provide element mapping of the independent claims to the applicant’s drawings. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended . The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3, 5-6, 8-9, 12-17 and 19-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Ju et al. (US 20210351303 A1, hereinafter Ju‘303) . Regarding independent claim 1 , Ju‘303 teaches, “An integrated circuit (fig. 1-28; ¶ [0025] - ¶ [0083]) comprising: a first semiconductor device (fig. 26A-26B, and fig. 5-4) having a first semiconductor region extending in a first direction from a first source or drain region (106), and a first gate structure (104) extending in a second direction over the first semiconductor region; a second semiconductor device (fig. 26B) having a second semiconductor region extending in the first direction from a second source or drain region (108), and a second gate structure (104) extending in the second direction over the second semiconductor region; a dielectric wall (126) extending in the first direction between the first gate structure (104) and the second gate structure (104) and between the first source or drain region (106) and the second source or drain region (108); and a conductive contact (120, fig. 26B, fig. 5) having a first region on a top surface of the first source or drain region (106), a second region that extends through a portion of the dielectric wall (126) along the second direction, a third region on a top surface of the second source or drain region (108), and a fourth region (fig. 26B) on a top surface of the first gate structure”. The instant claim does not define the relative direction of ‘a first direction’ and ‘a second direction’. These two directions can be explained as parallel, or opposite or perpendicular to each other using broadest reasonable interpretation (BRI). During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). Also, the instant claim uses the limitataion “on” which can be explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or bottom or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object. Regarding claim 3 , Ju‘303 further teaches, “The integrated circuit of claim 1, wherein a top surface of each of the first region, second region, third region, and fourth region of the conductive contact (120, fig. 26B, fig. 5) are substantially coplanar”. Regarding claim 5 , Ju‘303 further teaches, “The integrated circuit of claim 1, wherein the first region, second region, third region, and fourth region of the conductive contact comprise a same conductive material (120, fig. 26B, fig. 5)”. Regarding claim 6 , Ju‘303 further teaches, “The integrated circuit of claim 1, wherein the fourth region of the conductive contact extends away from the first region of the conductive contact along the first direction (120, fig. 26B, fig. 5)”. Regarding independent claim 8 , Ju‘303 teaches, “an electronic device (chip, ¶ [0002]), comprising: a chip package comprising one or more dies, at least one of the one or more dies (interconnected devices, ¶ [0002]) comprising (fig. 1-28; ¶ [0025] - ¶ [0083]) a first semiconductor device (fig. 26A-26B, and fig. 5-4) having a first semiconductor region extending in a first direction from a first source or drain region (106), and a first gate structure (104) extending in a second direction over the first semiconductor region; a second semiconductor device (fig. 26B) having a second semiconductor region extending in the first direction from a second source or drain region (108), and a second gate structure (104) extending in the second direction over the second semiconductor region; a gate cut (126) extending in the first direction (X) between the first gate structure (104) and the second gate structure (104) and between the first source or drain region (106) and the second source or drain region (106); and a conductive contact (120, fig. 26B, fig. 5) having a first region on a top surface of the first source or drain region (106), a second region that extends through a portion of the gate cut (126) along the second direction, a third region on a top surface of the second source or drain region (108), and a fourth region (fig. 26B) on a top surface of the first gate structure”. The instant claim does not define the relative direction of ‘a first direction’ and ‘a second direction’. These two directions can be explained as parallel, or opposite or perpendicular to each other using broadest reasonable interpretation (BRI). During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). Also, the instant claim uses the limitataion “on” which can be explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or bottom or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object. Regarding claim 9 , Ju‘303 further teaches, “The electronic device of claim 8, wherein respective top surfaces of the first region, second region, third region, and fourth region of the conductive contact (120, fig. 26B, fig. 5) are substantially coplanar, and below a first interconnect layer (122)”. Regarding claim 12 , Ju‘303 further teaches, “The electronic device of claim 8, wherein the first region, second region, third region, and fourth region of the conductive contact comprise a same conductive material (120, fig. 26B, fig. 5)”. Regarding claim 13 , Ju‘303 further teaches, “The electronic device of claim 8, wherein the fourth region of the conductive contact extends away from the first region of the conductive contact along the first direction (120, fig. 26B, fig. 5)”. Regarding independent claim 14 , Ju‘303 teaches, “An integrated circuit (fig. 1-28; ¶ [0025] - ¶ [0083]) comprising: a first semiconductor device (fig. 26A-26B, and fig. 5-4) having a first semiconductor region extending in a first direction from a first source or drain region (106), and a first gate structure (104) extending in a second direction over the first semiconductor region; a second semiconductor device (fig. 26B) having a second semiconductor region extending in the first direction from a second source or drain region (108), and a second gate structure (104) extending in the second direction over the second semiconductor region; a dielectric wall (126) extending in the first direction between the first gate structure (104) and the second gate structure (104) and between the first source or drain region (106) and the second source or drain region (108); a first conductive structure (part of element 120, fig. 26B, fig. 5) on a top surface of the first source or drain region (106); a second conductive structure (part of element 120, fig. 26B, fig. 5) on a top surface of the second source or drain region (106); a third conductive structure (part of element 120, fig. 26B, fig. 5) extending between the first conductive structure and the second conductive structure; and a fourth conductive structure (part of element 120, fig. 26B, fig. 5) extending from the first conductive structure and on a top surface of the first gate structure (104)”. The instant claim does not define the relative direction of ‘a first direction’ and ‘a second direction’. These two directions can be explained as parallel, or opposite or perpendicular to each other using broadest reasonable interpretation (BRI). During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). Also, the instant claim uses the limitataion “on” which can be explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or bottom or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object. Regarding claim 15 , Ju‘303 further teaches, “The integrated circuit of claim 14, wherein the first semiconductor device, second semiconductor device, first conductive structure, second conductive structure, third conductive structure, and fourth conductive structure are part of a device layer (120, fig. 26B, fig. 5) that is below an interconnect structure (122) that includes one or more interconnect layers”. Regarding claim 16 , Ju‘303 further teaches, “The integrated circuit of claim 14, wherein the third conductive structure extends through the dielectric wall between the first conductive structure and the second conductive structure (120, fig. 26B, fig. 5)”. Regarding claim 17 , Ju‘303 further teaches, “The integrated circuit of claim 14, wherein respective top surfaces of the first conductive structure, second conductive structure, third conductive structure, and fourth conductive structure (120, fig. 26B, fig. 5) are substantially coplanar”. Regarding claim 19 , Ju‘303 further teaches, “The integrated circuit of claim 14, wherein each of the first conductive structure, second conductive structure, third conductive structure, and fourth conductive structure comprise a same conductive material (120, fig. 26B, fig. 5)”. Regarding claim 20 , Ju‘303 further teaches, “The integrated circuit of claim 14, wherein the fourth conductive structure extends away from the first conductive structure along the first direction” (120, fig. 26B, fig. 5) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim s 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ju‘303 as applied to claim 1 as above, and further in view of Guha et al. (US 20210193836 A1, hereinafter Guha‘836) . Regarding claim 2 , Ju‘303 teaches all the limitations described in claim 1. Ju‘303 further teaches, wherein the first semiconductor region and the second semiconductor region comprise a plurality of semiconductor nanowires (fig. 1, ¶ [0024]) But Ju‘303 is silent upon the provision of wherein the first semiconductor region and the second semiconductor region comprise a plurality of semiconductor nanoribbons. However, Guha‘836 teaches a similar gate-all-around (GAA) integrated circuit structure uses semiconductor nanowire or nanoribbons (fig. 2C; ¶ [0045]) Ju‘303 and Guha‘836 are analogous art because they both are directed to GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ju‘303 with the features of Guha‘836 because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Ju‘303 and Guha‘836 to use nanoribbon to form the GAA device according to the teachings of Guha‘836 with a general motivation of exploiting the advantages of nanoribbon e.g., reduced leakage, high current mobility, better gate control etc. Regarding claim 7 , Ju‘303 modified with Guha‘836 further teaches, “A printed circuit board comprising the integrated circuit of claim 1 (fig. 9; ¶ [0136]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 10-11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claim 4 , the prior arts of record do not anticipate or make obvious, inter alia, the feature of: “ wherein the first region and the third region comprise a first conductive material, and the second region and the fourth region comprise a second conductive material different from the first conductive material” . Regarding dependent claim 10 , the prior arts of record do not anticipate or make obvious, inter alia, the feature of: “ wherein the first region and the third region comprise a first conductive material, and the second region and the fourth region comprise a second conductive material different from the first conductive material ”. Regarding dependent claim 18 , the prior arts of record do not anticipate or make obvious, inter alia, the feature of: “ wherein the first conductive structure and the second conductive structure comprise a first conductive material, and the third conductive structure and the fourth conductive structure comprise a second conductive material different from the first conductive material ” . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817 Application/Control Number: 18/125,455 Page 2 Art Unit: 2817 Application/Control Number: 18/125,455 Page 3 Art Unit: 2817 Application/Control Number: 18/125,455 Page 4 Art Unit: 2817 Application/Control Number: 18/125,455 Page 5 Art Unit: 2817 Application/Control Number: 18/125,455 Page 6 Art Unit: 2817 Application/Control Number: 18/125,455 Page 7 Art Unit: 2817 Application/Control Number: 18/125,455 Page 8 Art Unit: 2817 Application/Control Number: 18/125,455 Page 9 Art Unit: 2817 Application/Control Number: 18/125,455 Page 10 Art Unit: 2817 Application/Control Number: 18/125,455 Page 11 Art Unit: 2817 Application/Control Number: 18/125,455 Page 12 Art Unit: 2817 Application/Control Number: 18/125,455 Page 13 Art Unit: 2817
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