DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 2/13/2026 is acknowledged.
Applicant amended claims 1, 3, 9, 12, 15, and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 8, 9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US 2021/0066289) (hereafter Noh), in view of Ching et al. (US 2014/0312432) (hereafter Ching).
Regarding claim 1, Noh discloses a semiconductor device, comprising:
a substrate 100 (Fig. 5D, paragraph 0039) provided with an active pattern AP1 (Fig. 5D, paragraph 0041);
a gate electrode GE (Fig. 5D, paragraph 0046) that runs across the active pattern AP1 (Fig. 5D) and extends in a first direction (horizontal direction in Fig. 5D);
source/drain patterns SD1 (Figs. 5C and 5A, paragraph 0055) on the active pattern AP1 (Fig. 5C) on opposite sides of the gate electrode GE (Fig. 5A); and
a channel pattern CH1 (Figs. 5A and 5D, paragraph 0074) between the source/drain patterns SD1 (Fig. 5A) and in the active pattern AP1 (Fig. 5D).
Noh does not disclose a buried layer below the source/drain patterns and the channel pattern, wherein the buried layer includes:
first segments between the source/drain patterns and the active pattern along a vertical direction perpendicular to a bottom surface of the substrate, and
a second segment between the channel pattern and the active pattern,
wherein the first segments have a first level,
wherein the second segment has a second level, and
wherein the first level is lower than the second level.
Ching discloses a buried layer (204g and 1502a in Fig. 16b, paragraphs 0044-0045) below the source/drain patterns (1202a and 1204a in Fig. 16b, paragraph 0042) and the channel pattern (206a and 210a in Fig. 16b, paragraph 0042), wherein the buried layer includes (204g and 1502a in Fig. 16b):
first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) between the source/drain patterns (1202a and 1204a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b; and see upper portion of 202 in Fig. 16a) along a vertical direction (vertical direction in fig. 16b) perpendicular to a bottom surface of the substrate (bottom portion of 202 in Fig. 16b; and see bottom portion of 202 in Fig. 16a), and
a second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) between the channel pattern (206a and 210a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b),
wherein the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) have a first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b),
wherein the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) has a second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b), and
wherein the first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b) is lower than the second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form a buried layer below the source/drain patterns and the channel pattern, wherein the buried layer includes: first segments between the source/drain patterns and the active pattern along a vertical direction perpendicular to a bottom surface of the substrate, and a second segment between the channel pattern and the active pattern, wherein the first segments have a first level, wherein the second segment has a second level, and wherein the first level is lower than the second level, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Regarding claim 2, Noh in view of Ching discloses the semiconductor device of claim 1, however Noh does not disclose the first level of the first segments is the average distance between the first segments and a bottom surface of the substrate, and the second level of the second segment is the average distance between the second segment and the bottom surface of the substrate.
Ching discloses the first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b) of the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) is the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and a bottom surface of the substrate (bottom portion of 202 in Fig. 16b; and see bottom portion of 202 in Fig. 16a), and the second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b) of the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) is the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and the bottom surface of the substrate (bottom portion of 202 in Fig. 16b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form the first level of the first segments is the average distance between the first segments and a bottom surface of the substrate, and the second level of the second segment is the average distance between the second segment and the bottom surface of the substrate, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Regarding claim 5, Noh in view of Ching discloses the semiconductor device of claim 1, however Noh does not disclose the first segments of the buried layer have a first thickness that is less than a second thickness of the second segment of the buried layer.
Ching discloses the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) of the buried layer (204g and 1502a in Fig. 16b) have a first thickness (thicknesses of portions of 204g contacting bottom surface of 204b in Fig. 16b) that is less than a second thickness of the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) of the buried layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form the first segments of the buried layer have a first thickness that is less than a second thickness of the second segment of the buried layer, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Regarding claim 6, Noh further discloses the semiconductor device of claim 1, further comprising a pair of gate spacers GS (Fig. 5A, paragraph 0048) on opposite sidewalls of the gate electrode GE (Fig. 5A), wherein top surfaces of the pair of gate spacers GS (Fig. 5A) are higher than a top surface of the gate electrode GE (Fig. 5A).
Regarding claim 8, Noh in view of Ching discloses the semiconductor device of claim 1, however Noh does not disclose the buried layer is spaced apart from the source/drain patterns.
Ching discloses the buried layer (204g and 1502a in Fig. 16b) is spaced apart from the source/drain patterns (1202a and 1204a in Fig. 16b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form the buried layer is spaced apart from the source/drain patterns, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Regarding claim 9, Noh in view of Ching discloses the semiconductor device of claim 1, however Noh does not disclose a distance in the vertical direction between the gate electrode and the buried layer is less than a vertical length of the source/drain patterns.
Ching discloses a distance in the vertical direction between the gate electrode (1602, 1604, and 1606 in Fig. 16b) and the buried layer (204g and 1502a in Fig. 16b) is less than a vertical length of the source/drain patterns (1202a and 1204a in Fig. 16b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form a distance in the vertical direction between the gate electrode and the buried layer is less than a vertical length of the source/drain patterns, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Regarding claim 15, Noh discloses a semiconductor device, comprising:
a substrate 100 (Fig. 5D, paragraph 0039) provided with a logic cell including a PMOSFET region PR (Fig. 5D, paragraph 0039) and an NMOSFET region NR (Fig. 5D, paragraph 0039) that are spaced apart from each other in a first direction D1 (Fig. 5D);
a device isolation layer ST (Fig. 5D, paragraph 0042) on the substrate 100 (Fig. 5D);
a first active pattern AP1 (Fig. 5D, paragraph 0041) in the PMOSFET region PR (Fig. 5D) and a second active pattern AP2 (Fig. 5D, paragraph 0041) in the NMOSFET region NR (Fig. 5D), the first AP1 (Fig. 5A) and second active patterns AP2 (Fig. 5B) extending in a second direction D2 (Figs. 5A and 5B), and an upper portion of each of the first AP1 (Fig. 5C) and second active patterns AP2 (Fig. 5C) protruding upwardly above the device isolation layer ST (Fig. 5C);
a gate electrode GE (Fig. 5D, paragraph 0046) that extends in the first direction D1 (Fig. 5D) and runs across the first AP1 (Fig. 5D) and second active patterns AP2 (Fig. 5D);
first source/drain patterns SD1 (Fig. 5C, paragraph 0055) on the first active pattern AP1 (Fig. 5D);
second source/drain patterns SD2 (Fig. 5C paragraph 0055) on the second active pattern AP2 (Fig. 5D);
a first channel pattern CH1 (Fig. 5A, paragraph 0046) between the first source/drain patterns SD1 (Fig. 5A);
a second channel pattern CH2 (Fig. 5B, paragraph 0046) between the second source/drain patterns SD2 (Fig. 5A);
a pair of gate spacers GS (Fig. 5A, paragraph 0048) on opposite sidewalls of the gate electrode GE (Fig. 5A), the pair of gate spacers GS (Fig. 5A) extending (see Fig. 5D, wherein the gate electrode GE extends in first direction D1; and see paragraph 0048, wherein “a pair of gate spacers GS may be disposed on opposite sidewalls of each of the gate electrodes GE”) in the first direction D1 (Fig. 5D);
a gate dielectric layer GI (Fig. 5A, paragraph 0050) on a bottom surface and side surfaces of the gate electrode GE (Fig. 5A);
an interlayer dielectric layer 120 (Fig. 5A, paragraph 0055) on the gate electrode GE (Fig. 5A) and the gate spacers GS (Fig. 5A);
an active contact AC (Fig. 5A. paragraph 0058) that penetrates the interlayer dielectric layer 120 (Fig. 5A) and is electrically connected to at least one of the first SD1 (Fig. 5A) and second source/drain patterns; and
a gate contact V1_b (Fig. 5A, paragraph 0064) that penetrates the interlayer dielectric layer 120 (Fig. 5A) and is electrically connected to the gate electrode GE (Fig. 5A).
Noh does not disclose a buried layer below the first and second source/drain patterns and below the first and second channel patterns;
wherein the buried layer includes:
first segments between the first active pattern and the first source/drain patterns, and between the second active pattern and the second source/drain patterns, along a vertical direction perpendicular to the first direction; and
second segments between the first channel pattern and the first active pattern and between the second channel pattern and the second active pattern,
wherein the first segments have a first level,
wherein the second segments have a second level, and
wherein the first level is lower than the second level.
Ching discloses a buried layer (204g and 1502a in Fig. 16b, paragraphs 0044-0045) below the first (1202a and 1204a in Fig. 16b, paragraph 0042) and second source/drain patterns (similar to 1202a and 1204a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) and below the first (206a and 210a in Fig. 16b, paragraph 0042) and second channel patterns (similar to 206a and 210a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a);
wherein the buried layer (204g and 1502a in Fig. 16b) includes:
first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b and similar to portions of 204g contacting bottom surface of 204b in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) between the first active pattern (upper portion of 202 in Fig. 16b; and see upper portion of 202 in Fig. 16a) and the first source/drain patterns (1202a and 1204a in Fig. 16b), and between the second active pattern (similar to upper portion of 202 in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) and the second source/drain patterns (similar to 1202a and 1204a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a), along a vertical direction (vertical direction in Fig. 16b) perpendicular to the first direction; and
second segments (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b and similar to 1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) between the first channel pattern (206a and 210a in Fig. 16b) and the first active pattern (upper portion of 202 in Fig. 16b) and between the second channel pattern (similar to 206a and 210a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) and the second active pattern (similar to upper portion of 202 in Fig. 16b at cross-sectional view with 1202b in Fig. 16a),
wherein the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b and similar to portions of 204g contacting bottom surface of 204b in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) have a first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b),
wherein the second segments (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b and similar to 1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b at cross-sectional view with 1202b in Fig. 16a) have a second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b), and
wherein the first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) is lower than the second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh to form a buried layer below the first and second source/drain patterns and below the first and second channel patterns; wherein the buried layer includes: first segments between the first active pattern and the first source/drain patterns, and between the second active pattern and the second source/drain patterns, along a vertical direction perpendicular to the first direction; and second segments between the first channel pattern and the first active pattern and between the second channel pattern and the second active pattern, wherein the first segments have a first level, wherein the second segments have a second level, and wherein the first level is lower than the second level, as taught by Ching, since the second isolation structure 1502a (Ching, Fig. 16b, paragraph 0045) provides isolation between the second channel 210a (Ching, Fig. 16b, paragraph 0045) and the substrate 202 (Ching, Fig. 16b, paragraph 0045), which inhibits bottom current leakage into the substrate 202 (Ching, Fig. 16b, paragraph 0045).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Noh in view of Ching as applied to claim 1 above, and further in view of Yuan et al. (US 2011/0097889) (hereafter Yuan).
Regarding claim 4, Noh in view of Ching discloses the semiconductor device of claim 1, however Noh and Ching do not disclose the second segment of the buried layer has a convex shape directed toward the gate electrode.
Yuan discloses the second segment 40 (Fig. 8B, paragraph 0025) of the buried layer 40 (Fig. 8B) has a convex shape directed toward the gate electrode 64 (Fig. 8B, paragraph 0025).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh in view of Ching to form the second segment of the buried layer has a convex shape directed toward the gate electrode, as taught by Yuan, since the parasitic gate capacitance (Yuan, paragraph 0027) of the FinFETs may be reduced, and the speed of the respective FinFETs may be increased.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Noh in view of Ching as applied to claims 6 and 15 above, and further in view of Ju et al. (US 2021/0134795) (hereafter Ju).
Regarding claim 7, Noh in view of Ching discloses the semiconductor device of claim 6, however Noh and Ching do not disclose the pair of gate spacers and the buried layer are formed of the same dielectric material layer.
Ju discloses the pair of gate spacers 126’ (Fig. 3K, paragraph 0022, wherein “silicon oxycarbide”) and the buried layer 137A1 (Fig. 3K, paragraph 0057, wherein “carbon-containing silicon oxide (SiOC)”) are formed of the same dielectric material layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh in view of Ching to form the pair of gate spacers and the buried layer are formed of the same dielectric material layer, as taught by Ju, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 17, Noh in view of Ching discloses the semiconductor device of claim 15, however Noh and Ching do not disclose the gate spacers and the buried layer are formed of the same dielectric material layer.
Ju discloses the pair of gate spacers 126’ (Fig. 3K, paragraph 0022, wherein “silicon oxycarbide”) and the buried layer 137A1 (Fig. 3K, paragraph 0057, wherein “carbon-containing silicon oxide (SiOC)”) are formed of the same dielectric material layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Noh in view of Ching to form the pair of gate spacers and the buried layer are formed of the same dielectric material layer, as taught by Ju, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Allowable Subject Matter
1. Claims 3, 10-14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 3 would be allowable because a prior art, Ching et al. (US 2014/0312432), discloses a buried layer (204g and 1502a in Fig. 16b, paragraphs 0044-0045) below the source/drain patterns (1202a and 1204a in Fig. 16b, paragraph 0042) and the channel pattern (206a and 210a in Fig. 16b, paragraph 0042), wherein the buried layer includes (204g and 1502a in Fig. 16b): first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) between the source/drain patterns (1202a and 1204a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b; and see upper portion of 202 in Fig. 16a) along a vertical direction (vertical direction in fig. 16b) perpendicular to a bottom surface of the substrate (bottom portion of 202 in Fig. 16b; and see bottom portion of 202 in Fig. 16a), and a second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) between the channel pattern (206a and 210a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b), wherein the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) have a first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b), wherein the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) has a second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b), and wherein the first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b) is lower than the second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b) but fails to disclose the first segments of the buried layer have inclined surfaces relative to a horizontal direction and have a wedge shape whose width decreases with respect to an increasing distance in the vertical direction away from the source/drain patterns. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device, comprising: the first segments of the buried layer have inclined surfaces relative to a horizontal direction and have a wedge shape whose width decreases with respect to an increasing distance in the vertical direction away from the source/drain patterns in combination with other elements of the base claim 1.
In addition, claim 10 would be allowable because a closest prior art, Noh et al. (US 2021/0134795), discloses a gate electrode GE (Fig. 5D, paragraph 0046) that runs across the active pattern AP1 (Fig. 5D) and extends in a first direction (horizontal direction in Fig. 5D) but fails to teach the second segment of the buried layer and the gate electrode are formed of the same conductive material. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device, comprising: the second segment of the buried layer and the gate electrode are formed of the same conductive material in combination with other elements of the base claim 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 11-14 depend on claim 10.
Furthermore, claim 16 would be allowable because a prior art, Ching et al. (US 2014/0312432), discloses a buried layer (204g and 1502a in Fig. 16b, paragraphs 0044-0045) below the source/drain patterns (1202a and 1204a in Fig. 16b, paragraph 0042) and the channel pattern (206a and 210a in Fig. 16b, paragraph 0042), wherein the buried layer includes (204g and 1502a in Fig. 16b): first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) between the source/drain patterns (1202a and 1204a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b; and see upper portion of 202 in Fig. 16a) along a vertical direction (vertical direction in fig. 16b) perpendicular to a bottom surface of the substrate (bottom portion of 202 in Fig. 16b; and see bottom portion of 202 in Fig. 16a), and a second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) between the channel pattern (206a and 210a in Fig. 16b) and the active pattern (upper portion of 202 in Fig. 16b), wherein the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) have a first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b), wherein the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) has a second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b), and wherein the first level (the average distance between the first segments (portions of 204g contacting bottom surface of 204b in Fig. 16b) and bottom portion of 202 in Fig. 16b) is lower than the second level (the average distance between the second segment (1502a and portion of 204g contacting bottom surface of 1502a in Fig. 16b) and bottom portion of 202 in Fig. 16b) but fails to disclose the buried layer has a constant thickness, and wherein the first segments of the buried layer have an inclined surface relative to the substrate and have a wedge shape whose width decreases with increasing distance in the vertical direction from the first and second source/drain patterns. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device, comprising: the buried layer has a constant thickness, and wherein the first segments of the buried layer have an inclined surface relative to the substrate and have a wedge shape whose width decreases with increasing distance in the vertical direction from the first and second source/drain patterns in combination with other elements of the base claim 15.
Claims 21-23 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Noh et al. (US 2021/0066289), discloses a gate electrode GE (Fig. 5D, paragraph 0046) that runs across the active pattern AP1 (Fig. 5D) and extends in a first direction (horizontal direction in Fig. 5D); a buried layer ST (Figs. 5C and 5D, paragraph 0042) below the source/drain patterns SD1 (Fig. 5C) and the channel pattern CH1 (Fig. 5D), wherein the buried layer ST (Figs. 5C and 5D) includes: first segments (portion of ST below SD1 in Fig. 5C) below the source/drain patterns SD1 (Fig. 5C); and a second segment (portion of ST below CH1 in Fig. 5D) below the channel pattern CH1 (Fig. 5D); and the first segments (portion of ST below SD1 in Fig. 5C) of the buried layer ST (Fig. 5C) are formed of a dielectric material (see paragraph 0048, wherein “silicon oxide layer”) but fails to teach the second segment of the buried layer and the gate electrode are formed of the same conductive material. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device, comprising: the second segment of the buried layer and the gate electrode are formed of the same conductive material in combination with other elements of claim 21.
A closest prior art, Noh et al. (US 2021/0066289), discloses a semiconductor device, comprising: a substrate 100 (Fig. 5D, paragraph 0039) provided with an active pattern AP1 (Fig. 5D, paragraph 0041); a gate electrode GE (Fig. 5D, paragraph 0046) that runs across the active pattern AP1 (Fig. 5D) and extends in a first direction (horizontal direction in Fig. 5D); source/drain patterns SD1 (Figs. 5C and 5A, paragraph 0055) on the active pattern AP1 (Fig. 5C) on opposite sides of the gate electrode GE (Fig. 5A); a channel pattern CH1 (Figs. 5A and 5D, paragraph 0074) between the source/drain patterns SD1 (Fig. 5A) and in the active pattern AP1 (Fig. 5D); and a buried layer ST (Figs. 5C and 5D, paragraph 0042) below the source/drain patterns SD1 (Fig. 5C) and the channel pattern CH1 (Fig. 5D), wherein the buried layer ST (Figs. 5C and 5D) includes: first segments (portion of ST below SD1 in Fig. 5C) below the source/drain patterns SD1 (Fig. 5C); and a second segment (portion of ST below CH1 in Fig. 5D) below the channel pattern CH1 (Fig. 5D), wherein the first segments (portion of ST below SD1 in Fig. 5C) have a first level (the average distance between the portion of ST below SD1 and the substate 100 in Fig. 5C) and are formed of a dielectric material (see paragraph 0048, wherein “silicon oxide layer”), wherein the second segment (portion of ST below CH1 in Fig. 5D) has a second level (the average distance between the portion of ST below CH1 and the substate 100 in Fig. 5D), and wherein the first level (the average distance between the portion of ST below SD1 and the substate 100 in Fig. 5C) is lower than the second level (the average distance between the portion of ST below CH1 and the substate 100 in Fig. 5D) but fails to teach the second segment of the buried layer and the gate electrode are formed of the same conductive material as the context of claim 21. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 22-23 depend on claim 21.
Response to Arguments
1. Applicant's arguments filed 2/13/2026 have been fully considered.
Applicant's arguments with respect to claims 1, 2, 4-9, 15, and 17 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813