DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, on pages 9 and 10 of the remarks filed on 6/7/2025 filed respect amended claim 31, claim 32 and claim 34 and with respect to the selection of the level of the forward current have been fully considered and are persuasive. The non-final rejection 6/8/2026 on previously pending claim 33 has been withdrawn.
Applicant’s arguments with respect to claims 1-14 and 16-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 31, 32 and 34 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 31, prior art failed to disclose or fairly suggest a method of testing surge current capability of a semiconductor device, comprising ,wherein the forward current is applied to the test active area for a predetermined time period, wherein a level of the forward current is selected based on a ratio of an area of the test active area to an area of the main active area and based on a rated operating current of the main active area, as amended on 6/8/2026 and as argued on pages 9 and 10 of the remarks filed on 6/8/2026. Claims 32 and 34 depend from claim 31 and hence are allowed for the same reason therein.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 16-29 are rejected under 35 U.S.C. 103 as being unpatentable over Kojima (20210226031) in view of Goerlach (DE102015221971) further in view of Okano (20190310306)
Regarding Claim 1, in Figs. 2 and 3 and in paragraphs 0012, 0013, 0015, 0100 and 0106, Kojima discloses a semiconductor device 40, comprising: a semiconductor layer 30 comprising a first area 10/14/20a and an edge termination area 20 outside the first area, wherein the semiconductor layer has a first conductivity type (n); an active area 10 in the first area; a test area (which could be taken any area, specifically for instance area 10/41/42 in Fig. 2 and/or 20a in Fig. 3) in the first area adjacent 10/14/20a the active area; a first anode contact 14/31/32/33 on the semiconductor layer in the active area; a second anode contact 14/31/32/33 on the semiconductor layer in the test area; and a cathode contact 19 in electrical contact with the semiconductor layer 30. Kojima fails to disclose the newly added limitation a first anode contact on the semiconductor layer in the active area, the first anode contact comprising a first metal pad on the semiconductor layer in the active area; a second anode contact on the semiconductor layer in the test area, the second anode contact comprising a second metal pad separate from the first metal pad and on the semiconductor layer in the test area. However, Goerlach et al. discloses a Schottky Diode structure where in Fig. 2 the separate regions are disclosed as 102 (i.e. test active area with anode contact) and 103 (active are with anode contact).
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention in Kojima to have two separate regions as taught by Goerlach et al. in order to increases the testability of the Schottky diode.
Kojima and Goerlach combination fails to disclose the required amended Schottky diode structure. However, Okano disclose a semiconductor device where in Figs. 14, 18, 23 and 25, the required Schottky diode structure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required amended Schottky diode structure in Kojima and Goerlach combination as taught by Okano in order to measure the characteristics of the Schottky diode structure.
(Please note the paragraphs 0078, 088 and 0159 of Kojima teach an SBD device)
Regarding Claim 2, in Kojima, the active area comprises a first plurality of junction shielding regions 13/21/22/23 in the semiconductor layer, the first plurality of junction shielding regions having a second conductivity type (p) opposite the first conductivity type; wherein the first anode contact 14/31/32/33 contacts (where the contact could be an indirect contact) the semiconductor layer and the first plurality of junction shielding regions.
Regarding Claim 3, in Kojima, the test area 10/41/42/20a comprises a second plurality of junction shielding regions 13/21/22/23 in the semiconductor layer, wherein the second anode contact 14/31/32/33 contacts (where the contact could be an indirect contact) the semiconductor layer and the second plurality of junction shielding regions.
Regarding Claim 4, in Kojima, the semiconductor layer 30 comprises an n-type semiconductor material, and wherein the first plurality of junction shielding regions 13/21/22/23 comprise p-type semiconductor areas.
Regarding Claim 5, in Kojima, the edge termination area 20 comprises a main edge termination area, the semiconductor device further comprising a test edge termination area outside the test area, wherein the test edge termination area is within the first area (one can take the left portion of element 20 to be the first area and the right portion of element 20 to be the second area)
Regarding Claim 6, in Figs. 1 and 2 of Kojima, the test edge termination area comprises a plurality of concentric rings of implanted regions having a second conductivity type, opposite the first conductivity type.
Regarding Claim 7, in Figs. 1 and 2 of Kojima, a spacing between adjacent ones of the plurality of concentric rings is non-uniform.
Regarding Claim 8, in Figs. 1 and 2 of Kojima, the spacing between adjacent ones of the plurality of concentric rings is greater in a middle portion of the test edge termination area and smaller in first portions of the test edge termination area near the active area and second portions of the test edge termination area near the test area (see w vs w2b in Fig. 3)
Regarding Claim 9, in Fig. 3 of Kojima, a conductive electrical connection between the first anode contact 14/31/32/33 and the second anode contact 14/31/32/33 (one can take for instance the stepped portion of 14/31/32/33 to be first/second anode contact)
Regarding Claim 10, in paragraphs 0085-0087 of Kojima, the conductive electrical connection comprises a wirebond.
Regarding Claim 11, in paragraphs 0085-0087of Kojima, the conductive electrical connection comprises a metal layer.
Regarding Claim 12, in Figs. 2 and 3 of Kojima, the first area has a generally rectangular shape, and wherein the test active area is located near a corner of the first area.
Regarding Claim 13, in Figs. 2 and 3 of Kojima, the first area has a generally rectangular shape, and wherein the test area is located near a middle of a side of the first area.
Regarding Claim 14, in paragraphs 0006, 0082 and 0124 of Kojima, an isolation ring outside the test area, wherein the isolation ring comprises a region of the semiconductor layer having the first conductivity type.
Regarding Claim 15, in paragraphs 0102, 0107 and 0160 of Kojima, the semiconductor device comprises a Schottky diode device or a metal-oxide semiconductor device.
Regarding Claim 16, in Figs. 2-15 and in paragraphs 0012, 0013, 0015, 0100 and 0106, Kojima discloses a method of manufacturing a semiconductor device, comprising: forming an edge termination area 20 in a semiconductor layer 30, wherein the edge termination area is outside a first area of the semiconductor layer, wherein the semiconductor layer has a first conductivity type (n); forming an active area 10 in the first area; forming a test area (which could be taken any area, specifically for instance area 10/41/42 in Fig. 2 and/or 20a in Fig. 3) in the first area adjacent the active area; forming a first anode contact 14/31/32/33 on the semiconductor layer in the active area; forming a second anode contact 14/31/32/33 (first and second area could be taken with respect to the stepped portion for example) on the semiconductor layer in the test area; and forming a cathode contact 19 in electrical contact with the semiconductor layer. Kojima fails to disclose the newly added limitation a first anode contact on the semiconductor layer in the active area, the first anode contact comprising a first metal pad on the semiconductor layer in the active area; a second anode contact on the semiconductor layer in the test area, the second anode contact comprising a second metal pad separate from the first metal pad and on the semiconductor layer in the test area. However, Goerlach et al. discloses a Schottky Diode structure where in Fig. 2 the separate regions are disclosed as 102 (i.e. test active area with anode contact) and 103 (active are with anode contact).
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention in Kojima to have two separate regions as taught by Goerlach et al. in order to increases the testability of the Schottky diode.
Kojima and Goerlach combination fails to disclose the required amended Schottky diode structure. However, Okano disclose a semiconductor device where in Figs. 14, 18, 23 and 25, the required Schottky diode structure is disclosed.
(Please note the paragraphs 0078, 088 and 0159 of Kojima teach an SBD device)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required amended Schottky diode structure in Kojima and Goerlach combination as taught by Okano in order to measure the characteristics of the Schottky diode structure.
Regarding Claim 17, in Kojima, forming a first plurality of junction shielding regions 13/21/22/23 in the semiconductor layer, the first plurality of junction shielding regions 13/21/22/23 having a second conductivity type (p) opposite the first conductivity type (n); wherein the first anode contact 14/31/32/33 contacts (which could be an indirect contact) the semiconductor layer and the first plurality of junction shielding regions 13/21/22/23.
Regarding Claim 18, in Kojima, forming a second plurality of junction shielding regions 13/21/2/23 in the semiconductor layer in the test area, wherein the second anode contact 14/31/32/33 contacts (which could be an indirect contact) the semiconductor layer and the second plurality of junction shielding regions 13/21/22/23.
Regarding Claim 19, in Kojima, the semiconductor layer 30 comprises an n-type semiconductor material, and wherein the junction shielding regions 13/21/22/23 comprise p-type semiconductor areas.
Regarding Claim 20, in Kojima, the edge termination area comprises a main edge termination area, the method further comprising forming a test edge termination area outside the test area, wherein the test edge termination area is within the area inside the main edge termination area (one can take the left portion of element 20 to be the first area and the right portion of element 20 to be the second area)
Regarding Claim 21, in Kojima, the test edge termination comprises a plurality of concentric rings of implanted areas having the second conductivity type (see Figs. 2 and 3 and w vs w2b in Fig. 3)
Regarding Claim 22, in Figs. 2 and 3 of Kojima, a spacing between adjacent ones of the plurality of concentric rings is non-uniform (see w vs w2b in Fig. 3)
Regarding Claim 23, in Kojima, the spacing between adjacent ones of the plurality of concentric rings is greater in a middle portion of the test edge termination area and smaller in first portions of the test edge termination area near the main active area and second portions of the test edge termination area near the test active area (see w vs w2b in Fig. 3)
Regarding Claim 24, in Kojima, forming a conductive electrical connection between the first anode contact and the second anode contact (see paragraphs 0085-0087)
Regarding Claim 25, in Kojima, the conductive electrical connection comprises a wirebond (see paragraphs 0085-0087).
Regarding Claim 26, in Kojima, the conductive electrical connection comprises a metal layer (see paragraphs 0085-0087)
Regarding Claim 27, in Goerlach Fig. 1, the first area 103 has a generally rectangular shape, and wherein the test area is located near a corner of the first area.
Regarding Claim 28, in Figs. 2 and 3 of Goerlach, the first area has a generally rectangular shape, and wherein the test area is located near a middle of a side of the first area.
Regarding Claim 29, in paragraphs 0006, 0082 and 0124 of Goerlach, forming an isolation ring outside the test area, wherein the isolation ring comprises a area of the semiconductor layer having the first conductivity type.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 7/3/2026
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