Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on 11/7/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-10, 12, 14, 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810.
Re Claim 1, Okuno teaches a semiconductor device (fig23 and 24), comprising:
a semiconductor layer (2, fig23, [158]) comprising an active area (area inside 92, fig24 and 3, [60]) and an edge termination area (area around 92, fig24 and fig3, [60]) outside the active area;
a first implanted region (60, fig24, [144]) within the active area at a surface of the semiconductor layer; and
an integrated test area (area under probe needle 21 in 2, fig25, [147]) in the semiconductor layer, wherein the integrated test area comprises a second implanted region (3, fig25, [144]) in the semiconductor layer.
Okuno does not explicitly show the test area is configured for a material analysis test to be performed thereon.
Mochizuki teaches maximum doping concentration measured (fig5-6) to reach a desirable range ([44]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno and Mochizuki to test the concentration of the doping region. The motivation to do so is to achieve a JBS diode with high reliability (Mochizuki, [44]).
Re claim 2, Okuno modified above teaches the semiconductor device of Claim 1, wherein the integrated test area is within the active area (fig24 and 25).
Re claim 4, Okuno modified above teaches the semiconductor device of Claim 1, wherein the semiconductor layer has a first conductivity type (2 n-, fig23, [58]) and wherein the first implanted region (60 p-type, fig24, [144]) and the second implanted region (3 p-type, fig25, [144]) have a second conductivity type opposite the first conductivity type.
Re claim 5, Okuno modified above teaches the semiconductor device of Claim 1, further comprising an anode contact (12 and 11, fig25, [158]) on the semiconductor layer in the active area, wherein the anode contact contacts the integrated test area (11 in contact with area in 2 under 21, fig25).
Re claim 7, Okuno modified above teaches the semiconductor device of Claim 5, wherein: the semiconductor layer has a first conductivity type (2 n-, fig23, [58]); the active area comprises a first plurality of junction shielding regions (60 p-type, fig24, [144]) in the semiconductor layer, the first plurality of junction shielding regions having a second conductivity type (p-type, [144]) opposite the first conductivity type (n-type, [58]); and wherein the anode contact contacts the semiconductor layer (11 in contact with 2, fig25), the first plurality of junction shielding regions (11 in contact with 60, fig25) and the integrated test area (11 in contact with area in side 92, fig24 and 25).
Re claim 8, Okuno modified above teaches the semiconductor device of Claim 1, wherein the semiconductor layer has a first conductivity type (2 n-, fig23, [58]), and wherein the integrated test area has the first conductivity type (part of 2 n- inside 92, fig23, [58]).
Re claim 9, Okuno modified above teaches the semiconductor device of Claim 1, wherein the semiconductor layer has a first conductivity type (2 n-, fig23, [58]), and wherein the integrated test area has a second conductivity type (60 and 3 p-type, fig24, [144]) opposite the first conductivity type.
Re claim 10, Okuno modified above teaches the semiconductor device of Claim 1, wherein the active area has a generally rectangular shape (area inside 92, fig24 and 3, [60]), and wherein the integrated test area is located near a center of the active area (area directly under 21 of layer in 2, fig25, [147]).
Re claim 12, Okuno modified above teaches the semiconductor device of Claim 1, wherein the active area has a generally rectangular shape (area inside 92, fig24 and 3, [60]), and wherein the integrated test area is located near a middle of a side of the active area (fig24).
Re claim 14, Okuno modified above teaches the semiconductor device of Claim 1, wherein the integrated test area is square in shape (fig23 and 24).
Re claim 16, Okuno modified above teaches the semiconductor device of Claim 1, wherein the semiconductor device comprises a Schottky diode device (SBD, fig23 and 24, [141]), a bipolar junction transistor, or a metal-oxide semiconductor device.
Re claim 18, Okuno fourth embodiment does not explicitly show teaches the semiconductor device of Claim 1, further comprising: an isolation region in the semiconductor layer, wherein the isolation region surrounds the second implanted region.
Okuno first embodiment teaches an isolation region (91, fig3, [59]) in the semiconductor layer, wherein the isolation region surrounds the second implanted region (3, fig3, [144]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a terminal breakdown voltage holding layer under the protective film. The motivation to do so is to alleviate electric field in the terminal region (Okuno, [59]).
Re claim 19, Okuno modified above teaches the semiconductor device of Claim 18, wherein the isolation region comprises a trench (91, fig3, [59]) in the semiconductor layer or a semi-insulating region in the semiconductor layer.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810 and Goerlach et al. CN107026140.
Re claim 3, Okuno does not explicitly show the semiconductor device of Claim 1, wherein the integrated test area is outside the active area.
Goerlach teaches forming an integrated test area (103, fig1, [6, 26]) outside the active area (102, fig1, [26]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno and Goerlach to add in an extra isolated test pad region on side of the main active area. The motivation to do so is to prevent damage to the device during stress test (Goerlach, [4]) and improve testability of the device (Goerlach, [11]).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810, Goerlach et al. CN107026140 and Umemura et al. US 2003/0034558.
Re claim 11, Okuno teaches the semiconductor device of Claim 1, wherein the active area has a generally rectangular shape (area inside 92, fig24 and 3, [60]).
Okuno does not explicitly show wherein the test active area is located near a corner of the active area.
Goerlach teaches forming an integrated test area (103, fig1, [6, 26]) is outside the active area (102, fig1, [26]).
Umemura teaches the test active area (TEG region 21, fig5, [54]) is located near a corner of the active area (2, fig5, [53]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki, Goerlach and Umemura to add in an extra isolated test pad region at a corner of the active area. The motivation to do so is to prevent damage to the device during stress test (Goerlach, [4]), improve testability of the device (Goerlach, [11]) and easily detect defect in a short time (Umemura, [7]).
Claim(s) 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810 and Zhao et al. US 2011/0037139.
Re claim 13, Okuno does not explicitly show the semiconductor device of Claim 1, wherein the integrated test area has an area of at least about 2500 µm2.
Zhao teaches a SBD with p well width 1~3µm and spacing 4~8µm (fig1, [33]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Zhao to adjust the grid spacing and active area size. The motivation to do so is to avoid obstructing current flow (Zhao, [33]), operate at high temperature and low on-state voltage (Zhao, [7]).
Re claim 15, Okuno does not explicitly show the semiconductor device of Claim 14, wherein a side length of the integrated test area is from about 50 µm to about 150 µm.
Zhao teaches a SBD with p well width 1~3µm and spacing 4~8µm (fig1, [33]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Zhao to adjust the grid spacing and active area size. The motivation to do so is to avoid obstructing current flow (Zhao, [33]), operate at high temperature and low on-state voltage (Zhao, [7]).
Claim(s) 6 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810 and Hiyoshi US 2018/0012957.
Re claim 6, Okuno does not explicitly show the semiconductor device of Claim 1, wherein the integrated test area has peripheral dimensions selected to permit a destructive material analysis test to be performed on the semiconductor layer within the integrated test area.
Hiyoshi teaches impurity concentration in each section measured by SIMS ([42]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Hiyoshi to test the concentration of the doping region with SIMS. The motivation to do so is to achieve a JBS diode with high reliability (Mochizuki, [44]).
Re claim 42, Okuno does not explicitly show the semiconductor device of Claim 1, wherein the material analysis test comprises a secondary ion mass spectrometry (SIMS) analysis test.
Hiyoshi teaches impurity concentration in each section measured by SIMS ([42]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Hiyoshi to test the concentration of the doping region with SIMS. The motivation to do so is to achieve a JBS diode with high reliability (Mochizuki, [44]).
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810 and Tao et al. US 2022/0310822.
Re claim 17, Okuno teaches the semiconductor device of Claim 1, further comprising: a metal layer (11, fig23, [119]) on the semiconductor layer, wherein the metal layer contacts the first implanted region (60, fig23, [144]); an insulating layer (92, fig24, [60]) on the second implanted region (50, fig24, [154]).
Okuno does not explicitly show wherein the second implanted region is insulated from the metal layer by the insulating layer.
Tao teaches a first implanted region (implanted region in contact with 32, fig34, [120]) within the active area at a surface of the semiconductor layer (20, fig34, [120]); an insulating layer (30, fig34, [120]) on the second implanted region (implanted region in contact with 30, fig34) in the integrated test area (region between breakdown voltage holding layer under 30 in fig34; space between 91 in Okuno fig3), wherein the second implanted region (implanted region in contact with 30, fig34) is insulated from the metal layer (32, fig34, [120]) by the insulating layer (30, fig34, [120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Tao to replace the terminal protective film 92 with 30, 50, 60 and 70 of Tao in fig34 . The motivation to do so is to prevent damage to the device during stress test (Tao, [120]).
Claim(s) 38 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Tao et al. US 2022/0310822.
Re claim 38, Okuno teaches a semiconductor device (fig23 and 24), comprising:
a semiconductor layer (2, fig23, [158]) comprising an active area (area inside 92, fig24 and 3, [60]) and an edge termination area (area around 92, fig24 and fig3, [60]) outside the active area;
a first implanted region (60, fig24, [144]) within the active area at a surface of the semiconductor layer; and
an integrated test area (region between 91 in fig3 and area under 21 in 2 in fig25, [147]) within the active area at the surface of the semiconductor layer,
wherein the integrated test area comprises a second implanted region (3, fig25, [144]) in the semiconductor layer.
Okuno does not explicitly show an insulating layer on the integrated test area.
Tao teaches a first implanted region (implanted region in contact with 32, fig34, [120]) within the active area at a surface of the semiconductor layer (20, fig34, [120]); an insulating layer (30, fig34, [120]) on the second implanted region (implanted region in contact with 30, fig34) in the integrated test area (region between breakdown voltage holding layer under 30 in fig34; space between 91 in Okuno fig3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno and Tao to replace the terminal protective film 92 with 30, 50, 60 and 70 of Tao in fig34 . The motivation to do so is to prevent damage to the device during stress test (Tao, [120]).
Re claim 39, Okuno teaches a semiconductor device (fig24 and 27), comprising:
a semiconductor layer (2, fig27, [74]) comprising an active area (area inside 92, fig24, [60]) and an edge termination area (area around 92, fig24, [60]) outside the active area;
a first implanted region (3, fig27, [76]) within the active area at a surface of the semiconductor layer;
an integrated test area (region between 91 in fig3 and area under 21 and 25 in 2 in fig27, [150, 152]) within the active area, wherein the integrated test area comprises a second implanted region (50, fig27, [154]) in the semiconductor layer;
a metal layer (11, fig27, [58]) on the semiconductor layer,
wherein the metal layer (11, fig27, [119]) contacts the first implanted region (3, fig13, [76]); and
an insulating layer (92, fig24, [60]) on the second implanted region (50, fig24, [154]).
Okuno does not explicitly show wherein the second implanted region is insulated from the metal layer by the insulating layer.
Tao teaches a first implanted region (implanted region in contact with 32, fig34, [120]) within the active area at a surface of the semiconductor layer (20, fig34, [120]); an insulating layer (30, fig34, [120]) on the second implanted region (implanted region in contact with 30, fig34) in the integrated test area (region between breakdown voltage holding layer under 30 in fig34; space between 91 in Okuno fig3), wherein the second implanted region (implanted region in contact with 30, fig34) is insulated from the metal layer (32, fig34, [120]) by the insulating layer (30, fig34, [120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno and Tao to replace the terminal protective film 92 with 30, 50, 60 and 70 of Tao in fig34 . The motivation to do so is to prevent damage to the device during stress test (Tao, [120]).
Claim(s) 40, 41 and 43-45 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. US 2019/0310306 in view of Mochizuki et al. US 2016/0005810 and Uchida et al. US 2020/0266268.
Re claim 40, Okuno does not explicitly show the semiconductor device of Claim 1, wherein the first implanted region and the second implanted region are formed using a same implantation process.
Okuno teaches p-type region 60 and p-type region 3 with equal dopant concentration ([144]).
Uchida teaches all ion implanted regions are formed using a same implantation process (154, 1520, 1510 and 1530, fig10, [91]) using mask 1600.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Uchida to form all p-type regions with a same implantation process with a same mask. The motivation to do so is to simplify production step (Uchida, [91])
Re claim 41, Okuno modified above teaches the semiconductor device of Claim 40, wherein the same implantation process is an ion implantation (Uchida, fig10, [91]).
Re claim 43, Okuno modified above teaches the semiconductor device of Claim 1, wherein the integrated test area is configured for testing prior to formation of an anode contact (Mochizuki, test the concentration of the doping region to achieve a JBS diode with high reliability, [44]).
Re claim 44, Okuno does not explicitly show the semiconductor device of Claim 7, wherein the integrated test area has substantially a same doping profile as the first plurality of junction shielding regions.
Okuno teaches p-type region 60 and p-type region 3 with equal dopant concentration ([144]).
Uchida teaches all ion implanted regions are formed using a same implantation process (154, 1520, 1510 and 1530, fig10, [91]) using mask 1600.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Okuno, Mochizuki and Uchida to form all p-type regions with a same implantation process with a same mask. The motivation to do so is to simplify production step (Uchida, [91])
Re claim 45, Okuno modified above teaches the semiconductor device of Claim 1, wherein the semiconductor layer comprises an n-type semiconductor material (2 n-, fig23, [58]), and wherein the integrated test area comprises a p- type semiconductor material (p-type region 60 and 3 with equal dopant concentration, fig24, [144]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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