Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-11 are presented for examination.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-11 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Fujiwara et al. US Pub. No. 20220139440.
As per claims 1, Fig. 4 or 7 of Fujiwara is directed to a system comprising: an array of non-volatile memory cells (145, Fig. 1, par. 17) arranged into rows and columns (Fig. 4 or 7); and a plurality of sets of two or more output lines (ARBL[0] and BRBL[0], (ARBL[1] and BRBL[1]), where each column (325, par. 38) contains a set of two or more output lines (ARBL[0] and BRBL[0]); wherein each row (WWL[0]) is coupled to only one output line (ARBL[0]) in the set of two or more output lines for each column.
As per claims 2-3, Fig. 4 or 7 of Fujiwara discloses wherein the output lines are bit lines (ARBL[0] and BRBL[0], par. 38).
As per claim 4, Fig. 4 or 7 of Fujiwara discloses wherein each set of two or more output lines in the plurality of sets of two or more output lines comprises four output lines (ARBL[0] and BRBL[0], (ARBL[1] and BRBL[1]).
As per claim 5, a paragraph 17 of Fujiwara discloses wherein the non-volatile memory cells are split-gate flash memory cells (other types of memory cells, par. 17).
As per claim 6, a paragraph 17 of Fujiwara discloses wherein the non-volatile memory cells are stacked-gate flash memory cells (other types of memory cells, par. 17).
As per claims 7-8 and 11, Fig. 4 or 7 of Fujiwara discloses an output driver (connecting to RWL) coupled to the plurality of sets of two or more output lines.
As per claim 9, Fig. 4 or 7 of Fujiwara discloses a third output driver (connecting to RWL of 340) coupled to a third line (ARBL[1] in 340) in each set of two or more output lines in the plurality of sets of two or more output lines; and a fourth output driver (connecting to RWL of 340) coupled to a fourth line (BRBL[1] in 340) in each set of two or more output lines in the plurality of sets of two or more output lines.
As per claim 10, a paragraph 17 of Fujiwara discloses a high voltage decoder (inherency in the flash memory, par. 17) for providing high voltages to the array during program and erase operations.
It is noted that claims 5-6 and 10 would be rejected under a 103 rejection in view of Tran et al. US Pub. No. 20200233482 by Fig. 2, Fig. 7 and a paragraph 137, respectively.
6. Claims 1-4, 6 and 10 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by La Rosa et al. US Pub. No. 20180151584.
As per claims 1 and 6, Fig. 4 of La Rosa is directed to a system comprising: an array of non-volatile memory cells (Fig. 4) arranged into rows and columns; and a plurality of sets of two or more output lines (B1,j and B2,j; and B1,j+1, B2,j+1), where each column contains a set of two or more output lines (B1,j and B2,j) ; wherein each row (CGL1) is coupled to only one output line (B1,j) in the set of two or more output lines for each column.
As per claims 2-3, a paragraph 91 and Fig. 4 of La Rosa disclose wherein the output lines are bit lines (B1,j and B2,j; and B1,j+1, B2,j+1).
As per claim 4, a paragraph 91 and Fig. 4 of La Rosa disclose wherein each set of two or more output lines in the plurality of sets of two or more output lines comprises four output lines (B1,j, B2,j, B1,j+1 and B2,j+1).
As per claim 10, a paragraph 91 and Fig. 4 of La Rosa disclose comprising: a high voltage decoder (RD1) for providing high voltages to the array during program and erase operations.
7. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827