DETAILED ACTION
This action is responsive to the following communication: the response filed 7/30/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-3, 5-6, 8, 17-19, 21-27 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 17-18, 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0392909 ‒hereinafter Yang) in view of Lee (US 2019/0115081).
Regarding claim 1, Yang discloses a memory device (fig. 12, 13), comprising:
a memory array (para 0367) including memory cells (MC(s); fig. 12);
bit lines (BL1-BLm; fig. 6) coupled to the memory cells;
word lines (WLL1-WLL48; fig. 6) coupled to the memory cells;
a column decoder (618; fig. 6) coupled to the bit lines (BLm);
a sensing circuit (620; fig. 6) coupled to the column decoder (618); and
a controller (600; fig. 6) coupled to the memory array and configured to:
perform a first verify operation (1st Verify Stage for a word line WLL1(s); fig. 12, 13) on a first memory cell (any memory cell of the MC(s) connected to WLL1(s)) of the memory cells by applying a first verify voltage (any of verify voltage(s) VvC-VvA to WLL1(s)) to a first word line coupled to the first memory cell (WLL1(s)); and
after performing the first verify operation (after the 1st Verify Stage for the word line WLL1(s) is completed; fig. 13), perform a second verify operation (2nd Verify Stage for another word line WLL2(s); fig. 12, 13) on a second memory cell (any memory cell of the MC(s) connected to WLL2(s)) of the memory cells by applying a second verify voltage (any of verify voltage(s) VvC-VvA to WLL2(s)) to a second word line coupled to the second memory cell (WLL2(s)),
wherein the first memory cell and the second memory cell are in a same block of the memory array (i.e. in a same sub-block of the array; fig. 12).
Yang does not expressly disclose according to a first develop time to the first memory cell for the first develop time; according to a second develop time to the second memory cell for the second develop time, wherein the second develop time is larger than the first develop time.
Lee discloses (in a verify interval; para 0124) according to a first develop time (DVL1 for a memory cell; fig. 24) to the first memory cell (any first memory cell, i.e. MC1; fig. 22) for the first develop time; according to a second develop time (DVL2 for another memory cell; fig. 24) to the second memory cell (any second memory cell, i.e. MC2; fig. 22) for the second develop time, wherein the second develop time is larger than the first develop time (second develop time DVL2 may be longer than the first develop time DVL1; para 0125).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lee for the purpose of checking word lines and memory blocks for defects using separate develop times while performing a write operation (para 0129-0130 of Lee), which is common and well known in the art for facilitating data accessing schemes by improving the overall performance speed to achieve a robust memory system.
Regarding claim 2, Yang discloses the memory device (fig. 12, 13), wherein the first verify operation (1st Verify Stage for the word line WLL1(s)) comprises a first coarse verify operation (i.e. for the 1st Verify Stage, any verify sub-stage VvC/VvB is considered a coarse verify operation, prior to a final verify VvA), and the second verify operation (2nd Verify Stage for the word line WLL2(s)) comprises a second coarse verify operation (i.e. for the 2nd Verify Stage, any verify sub-stage VvC/VvB is considered a coarse verify operation, prior to a final verify VvA).
Regarding claim 3, Yang discloses the memory device (fig. 12, 13), wherein the memory array further comprises a memory string (para 0178), the memory string comprises the first memory cell corresponding to a first word line (any memory cell of the MC(s) connected to WLL1(s)) and the second memory cell corresponding to a second word line (any memory cell of the MC(s) connected to WLL2(s)).
Regarding claim 17, Yang discloses a method for operating a memory device (fig. 12, 13), comprising:
performing a first verify operation (1st Verify Stage for a word line WLL1(s); fig. 12, 13) on a first memory cell of memory cells (any memory cell of the MC(s) connected to WLL1(s)) of a memory array (para 0367) by applying a first verify voltage (any of verify voltage(s) VvC-VvA to WLL1(s)) to a first word line coupled to the first memory cell (WLL1(s)); and
after performing the first verify operation (after the 1st Verify Stage for the word line WLL1(s) is completed; fig. 13), performing a second verify operation (2nd Verify Stage for another word line WLL2(s); fig. 12, 13) on a second memory cell of the memory cells (any memory cell of the MC(s) connected to WLL2(s)) by applying a second verify voltage (any of verify voltage(s) VvC-VvA to WLL2(s)) to a second word line coupled to the second memory cell (WLL2(s)), wherein the first memory cell and the second memory cell are in a same block of the memory array (i.e. in a same sub-block of the array; fig. 12).
Yang does not expressly disclose according to a first develop time to the first memory cell for the first develop time; according to a second develop time by applying to the second memory cell for the second develop time, wherein the second develop time is larger than the first develop time.
Lee discloses (in a verify interval; para 0124) according to a first develop time (DVL1 for a memory cell; fig. 24) to the first memory cell (any first memory cell, i.e. MC1; fig. 22) for the first develop time; according to a second develop time (DVL2 for another memory cell; fig. 24) to the second memory cell (any second memory cell, i.e. MC2; fig. 22) for the second develop time, wherein the second develop time is larger than the first develop time (second develop time DVL2 may be longer than the first develop time DVL1; para 0125).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lee for the purpose of checking word lines and memory blocks for defects using separate develop times while performing a write operation (para 0129-0130 of Lee), which is common and well known in the art for facilitating data accessing schemes by improving the overall performance speed to achieve a robust memory system.
Regarding claim 18, Yang discloses the method, wherein the memory array further comprises a memory string (para 0178), the memory string comprises the first memory cell corresponding to the first word line (any memory cell of the MC(s) connected to WLL1(s)), and the second memory cell corresponding to the second word line (any memory cell of the MC(s) connected to WLL2(s)).
Regarding claim 21, Yang discloses the memory device, wherein the memory array comprises a plurality of blocks, each of the plurality of blocks comprises a common source line (SL; fig. 6).
Regarding claim 22, Yang discloses the memory device, wherein the first memory cell and the second memory cell on the same block are configured to be erased at the same time (para 0085).
Regarding claim 23, Yang discloses the memory device, wherein the first memory cell and the second memory cell are in different groups of word lines on the same block (fig. 12).
Claim(s) 5-6, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0392909 ‒hereinafter Yang) in view of Lee (US 2019/0115081), and further in view of Sim et al. (US 2013/0194872 ‒hereinafter Sim).
Regarding claim 5, Yang discloses the memory device (fig. 12, 13), wherein performing the first verify operation on the first memory cell of the memory cells (i.e. of WLL1(s)), and performing the second verify operation on the second memory cell of the memory cells (i.e. of WLL2(s)).
Yang does not expressly disclose according to the first develop time is under a first temperature; according to the second develop time is under a second temperature, wherein the first temperature is different from the second temperature.
Lee discloses (in a verify interval; para 0124) according to the first develop time (DVL1 for a memory cell; fig. 24); according to the second develop time (DVL2 for another memory cell; fig. 24).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lee for the purpose of checking word lines and memory blocks for defects using separate develop times while performing a write operation (para 0129-0130 of Lee), which is common and well known in the art for facilitating data accessing schemes by improving the overall performance speed to achieve a robust memory system.
Sim discloses [the first develop time] is under a first temperature (low temperature sensing having first develop time tDEV_L; fig. 4B), and [the second develop time] is under a second temperature (high temperature sensing having first develop time tDEV_H; fig. 4A), wherein the first temperature is different from the second temperature (para 0068).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Sim for the purpose of facilitating data accessing schemes by in which disturbances due to temperature fluctuations may be minimized (para 0077-0079 of Sim), which predicts the commonly understood advantage of securing the integrity of data storage.
Regarding claim 6, Sim discloses the memory device, wherein the first develop time is longer than the second develop time, and the first temperature is lower than the second temperature (para 0077, 0079).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Sim for the purpose of facilitating data accessing schemes by in which disturbances due to temperature fluctuations may be minimized (para 0077-0079 of Sim), which predicts the commonly understood advantage of securing the integrity of data storage.
Regarding claim 19, Yang discloses the memory device (fig. 12, 13), wherein performing the first verify operation on the first memory cell of the memory cells (i.e. of WLL1(s)), and performing the second verify operation on the second memory cell of the memory cells (i.e. of WLL2(s)).
Yang does not expressly disclose according to the first develop time is under a first temperature; according to the second develop time is under a second temperature, wherein the first develop time is longer than the second develop time, and the first temperature is lower than the second temperature.
Lee discloses (in a verify interval; para 0124) according to the first develop time (DVL1 for a memory cell; fig. 24); according to the second develop time (DVL2 for another memory cell; fig. 24).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lee for the purpose of checking word lines and memory blocks for defects using separate develop times while performing a write operation (para 0129-0130 of Lee), which is common and well known in the art for facilitating data accessing schemes by improving the overall performance speed to achieve a robust memory system.
Sim discloses [the first develop time] is under a first temperature (low temperature sensing having first develop time tDEV_L; fig. 4B), and [the second develop time] is under a second temperature (high temperature sensing having first develop time tDEV_H; fig. 4A), wherein the first temperature is different from the second temperature (para 0068), wherein the first develop time is longer than the second develop time, and the first temperature is lower than the second temperature (para 0077, 0079).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Sim for the purpose of facilitating data accessing schemes by in which disturbances due to temperature fluctuations may be minimized (para 0077-0079 of Sim), which predicts the commonly understood advantage of securing the integrity of data storage.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0392909 ‒hereinafter Yang) in view of Lee (US 2019/0115081), and further in view of Lee (US 2012/0069674 ‒hereinafter Lee ‘9674).
Regarding claim 8, Yang, as modified, does not expressly disclose the memory device, wherein the first verify operation comprises a 3 bit line (3BL) coarse verify operation, and the second verify operation comprises a 3BL fine verify operation.
Lee ‘9674 discloses first verify operation comprises a 3 bit line (3BL) coarse verify operation (“coarse sensing operation, a precharge voltage is applied to all of the selected bit lines” para 0034, which may essentially comprises at least 3 bit lines BL0-BL3; fig. 3), and the second verify operation comprises a 3BL fine verify operation (“fine sensing scheme according to some embodiments, a predetermined voltage is applied to a selected word line and a precharge voltage is applied to all bit lines connected to the selected memory cells” para 0033, which essentially comprises at least 3 bit lines BL0-BL3; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Lee ‘9674 for the purpose of improving the overall reliability of the device by reducing noise and disturbances (para 0010 of Lee ‘9674), and to try the modification for the additional purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0392909 ‒hereinafter Yang) in view of Lee (US 2019/0115081), and further in view of Tang et al. (US 2018/0254089 “Tang”).
Regarding claim 24, Yang, as modified, does not expressly disclose the memory device, wherein the first develop time and the second develop time are determined by discharging a sense out (SO) node capacitor corresponding to a selected bit line.
Tang discloses the first develop time and the second develop time (i.e. respective of first and second memory cells; fig. 4 para 0065+) are determined by discharging a sense out (SO) node capacitor corresponding to a selected bit line (fig. 3 para 0070).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by avoiding non-linearity factors resulting from a negative voltage across capacitance (para 0070 of Tang), which is common and well known in the art to secure the integrity of data storage.
Claim(s) 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0392909 ‒hereinafter Yang) in view of Lee (US 2019/0115081), in view of Tang et al. (US 2018/0254089 “Tang”), and further in view of Yano (US 2017/0140826).
Regarding claim 25, Yang, as modified, does not expressly disclose the memory device, wherein the first memory cell and the second memory cell are connected to the SO node capacitor.
Yano discloses the first memory cell and the second memory cell are connected to the SO node capacitor (fig. 1, 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Yano for the purpose of facilitating data accessing schemes by decreasing coupling disturbances in the circuit (para 0031+ of Yano), as is consistent with known practices in the prior art.
Regarding claim 26, Yano discloses the memory device, wherein the first memory cell and the second memory cell are connected to the SO node capacitor of the same sensing circuit (fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Yano for the purpose of facilitating data accessing schemes by decreasing coupling disturbances in the circuit (para 0031+ of Yano), as is consistent with known practices in the prior art.
Regarding claim 27, Yang discloses the memory device of claim 1, wherein the controller further configured to: perform the first verify operation on a first group of memory cells of the memory cells by applying the first verify voltage coupled to the first group of memory cells; and after performing the first verify operation, perform a second verify operation on a second group of memory cells of the memory cells by applying the second verify voltage coupled to the second group of memory cells, wherein the first group of memory cells and the second group of memory cells are in a same block of the memory array (fig. 13).
Yang does not expressly disclose according to the first develop time to a first group of word lines for the first develop time; according to the second develop time to a second group of word lines for the second develop time.
Lee discloses according to the first develop time; according to the second develop time (fig. 22).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lee for the purpose of checking word lines and memory blocks for defects using separate develop times while performing a write operation (para 0129-0130 of Lee), which is common and well known in the art for facilitating data accessing schemes by improving the overall performance speed to achieve a robust memory system.
Yano discloses to a first group of word lines; to a second group of word lines (fig. 4-6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Yano for the purpose of facilitating data accessing schemes by decreasing coupling disturbances in the circuit (para 0031+ of Yano), as is consistent with known practices in the prior art.
Response to Arguments
Applicant's arguments filed 7/30/26 have been fully considered but are not persuasive.
The applicant submits that the combined references of Yang et al. (US 2019/0392909 “Yang”) and Lee (US 2019/0115081) fails to disclose applying different development times to memory cells located on different word lines, as Lee’s first and second memory cells are coupled to a same word line (on page 7 of the response, regarding the pending claim(s)).
The examiner respectfully disagrees with the arguments. MPEP § 2144 discusses supporting a rejection under 35 U.S.C. 103, with MPEP § 2144(I) specifically noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law.
In the previous Office Action, the examiner has provided the motivation to combine that using different development times to different memory cells (i.e. develop times DVL1 and DVL2; Lee, fig. 24) would check word lines and memory blocks for defects, which facilitates data accessing schemes such as disclosed by Yang (i.e. 1st verify stage for a word line and 2nd verify stage for another word line; Yang, fig. 13). This rationale to combine the references is reasoned from common knowledge in the art, as a person of ordinary skill is also a person of ordinary creativity, not an automaton, and in many cases will be able to fit teachings of multiple patents together like pieces of a puzzle (See MPEP § 2141.03). Therefore, a person of ordinary skill in the art would recognized that the different memory cells of Lee having different develop times, although coupled to the same word line, is an augmentation to the different memory cells of Yang coupled to different word lines (i.e. during different verify stages; Yang, fig. 13).
It is recognized so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, such an augmentation is considered proper. For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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