Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4, 8, 11, and 15 were withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on September 17th, 2025.
Applicant's election with traverse of Species A in the reply filed on September 17th, 2025, is acknowledged. The traversal is on the grounds that at least examining Species A, C, and D would not appear to impose an examination and search burden. This is found persuasive.
The restriction requirement filed July 17th, 2025, has been overcome and is withdrawn. Claims 4, 8, 11, and 15 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 24th, 2023, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In this instance, Claim 8 recites the limitation “a lowermost surface of the first portion of the upper source/drain region is between an upper surface of the first nanosheet and the lower surface of the second nanosheet”. Applicant’s filed specification states ([0122], see fig. 34) “the lowermost surface 640a of the first portion 641 of the upper source/drain region 640 may be formed lower than the upper surface 111b of the first nanosheet 111”. Therefore, the applicant has support for forming the lowermost surface of the first portion of the upper source/drain region is below an upper surface of the first nanosheet and above a lower surface of the first nanosheet, but does not provide support for the claimed limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (2023/0028900 A1; hereinafter Lin).
Regarding Claim 12, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D), a second nanosheet (middle 106a, see figs. 1A and 1D), and a third nanosheet (top most 106a, see figs. 1A and 1D) sequentially stacked on the active pattern (active pattern) in a vertical direction (Z, see fig. 1A), the first nanosheet (bottom 106a), the second nanosheet (middle 106a), and the third nanosheet (top 106a) being spaced apart from each other in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first to third nanosheets (bottom 106a, middle 106a, top 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), an uppermost surface of the lower source/drain region (top of 118A) being lower (see fig. 1A) than a lower surface of the second nanosheet (bottom of middle 106a), and the lower source/drain region (118a) not being doped with an impurity ([0070], 118a may not be doped);
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region (118a), the upper source/drain region (110a) being doped with a second impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118c and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
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Annotated Figure 1D
Regarding Claim 13, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, further comprising an interlayer insulation layer ([0051]-[0052], 134, 136, see fig. 1C) in contact with each of a sidewall of the lower source/drain region (118a) and a sidewall of the upper source/drain region (110a).
Regarding Claim 14, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, wherein an uppermost surface of the lower source/drain region (top of 118a) is lower (see fig. 1A) than a lower surface of the first nanosheet (bottom of bottom 106a).
Regarding Claim 15, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, wherein an uppermost surface of the lower source/drain region (top of 118a) is higher ([0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of 106a) than an upper surface of the first nanosheet (top of bottom 106a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Mochizuki et al (2019/0348403 A1; hereinafter Mochizuki).
Regarding Claim 1, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D) spaced apart from the active pattern (active pattern) in a vertical direction (Z, see fig. 1A);
a second nanosheet (middle 106a, see figs. 1A and 1D) spaced apart from the first nanosheet (bottom 106a) in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), an uppermost surface of the lower source/drain region (top of 118A) being lower (see fig. 1A) than a lower surface of the second nanosheet (bottom of middle 106a), and [];
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region (118a), the upper source/drain region (110a) being doped with a third impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118c and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
Lin doesn’t teach the lower source/drain region being doped with a second impurity having the first conductivity type.
However, Mochizuki (fig. 10) teaches the lower source/drain region ([0042], 160) being doped with a second impurity ([0043], 160 is counter-doped to the source/drain regions 165, therefore 160 may be doped N type when 165 is doped P type) having the first conductivity type (N). Mochizuki also teaches that the counter doped regions prevent shorts and reduce leakage ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Lin to include the counter doped lower source/drain region of Mochizuki to reduce leakage.
Regarding Claim 2, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, further comprising an interlayer insulation layer ([0051]-[0052], 134, 136, see fig. 1C) in contact with each of a sidewall of the lower source/drain region (118a) and a sidewall of the upper source/drain region (110a).
Regarding Claim 3, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the uppermost surface of the lower source/drain region (top of 118a) is lower (see fig. 1A) than a lower surface of the first nanosheet (bottom of bottom 106a).
Regarding Claim 4, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the uppermost surface of the lower source/drain region (top of 118a) is higher ([0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of bottom 106c, see fig. 2J) than an upper surface of the first nanosheet (top of bottom 106a).
Regarding Claim 9, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein at least a portion of the upper source/drain region (110a) overlaps (see fig. 1C) the active pattern (active pattern) in the first horizontal direction (X).
Regarding Claim 10, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the upper source/drain region (110a) is in contact with each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a).
Regarding Claim 11, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the lower source/drain region (118a) is in contact ([0042], [0044], transistor 104c shows that 118c and bottom 106c may be in contact) with the first nanosheet (bottom 106a), and the upper source/drain region (110a) is in contact with the second nanosheet (middle 106a).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Mochizuki as applied to Claim 1 above, and further in view of (2023/0178600 A1; hereinafter Chuang).
Regarding Claim 5, Lin doesn’t teach the semiconductor device as claimed in claim 1, wherein the upper source/drain region includes a first portion surrounded by the lower source/drain region and a second portion on the first portion, the second portion being in contact with the second nanosheet.
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion, the second portion (second portion) being in contact with the second nanosheet ([0075], middle 108a, see fig. 5A-1). Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
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Annotated Figure 5A-2
Regarding Claim 6, Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, wherein a width in the second horizontal direction of the first portion (width of first portion in the left to right direction, see annotated fig. 5A-2) of the upper source/drain region (168a) is smaller (since the first portion is curved it has a portion that has a smaller width than the active pattern) than a width in the second horizontal direction of the active pattern ([0053], portion of substrate 102 between 116, see fig. 2K).
Regarding Claim 7, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, wherein a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is lower (Lin, bottom of 110a) than a lower surface of the first nanosheet (Lin, bottom of bottom 106a).
Regarding Claim 8, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is between (Lin, [0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of bottom 106c, see fig. 2J) an upper surface of the first nanosheet (Lin, top of bottom 106a) and the lower surface of the second nanosheet (bottom of middle 106a).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to Claim 12 above, and further in view of Chuang.
Regarding Claim 16, Lin doesn’t teach the semiconductor device as claimed in claim 12, wherein the upper source/drain region includes a first portion surrounded by the lower source/drain region and a second portion on the first portion, the second portion being in contact with the second nanosheet.
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion, the second portion (second portion) being in contact with the second nanosheet ([0075], middle 108a, see fig. 5A-1). Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Mochizuki and Chuang.
Regarding Claim 17, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D) spaced apart from the active pattern (active pattern) in a vertical direction (Z, see fig. 1A);
a second nanosheet (middle 106a, see figs. 1A and 1D) spaced apart from the first nanosheet (bottom 106a) in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), and [];
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region (118a), the upper source/drain region (110a) being doped with a third impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N) [], and the upper source/drain region (110a) being in contact with the second nanosheet (middle 106a); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118c and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
Lin doesn’t teach the lower source/drain region being doped with a second impurity having the first conductivity type.
However, Mochizuki (fig. 10) teaches the lower source/drain region ([0042], 160) being doped with a second impurity ([0043], 160 is counter-doped to the source/drain regions 165, therefore 160 may be doped N type when 165 is doped P type) having the first conductivity type (N). Mochizuki also teaches that the counter doped regions prevent shorts and reduce leakage ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Lin to include the counter doped lower source/drain region of Mochizuki to reduce leakage.
Lin doesn’t teach the upper source/drain region including a first portion surrounded by the lower source/drain region and a second portion on the first portion
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion. Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 18, Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 17, wherein a width in the second horizontal direction of the first portion (width of first portion in the left to right direction, see annotated fig. 5A-2) of the upper source/drain region (168a) is smaller (since the first portion is curved it has a portion that has a smaller width than the active pattern) than a width in the second horizontal direction of the active pattern ([0053], portion of substrate 102 between 116, see fig. 2K).
Regarding Claim 19, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 17, wherein a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is lower (Lin, bottom of 110a) than a lower surface of the first nanosheet (Lin, bottom of bottom 106a).
Regarding Claim 20, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 17, wherein at least a portion of the upper source/drain region (110a) overlaps (see fig. 1C) the active pattern (active pattern) in the first horizontal direction (X).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 15, 2026