Detailed Action
This office action is in response to the amendment filed on April 16th, 2026. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 30th, 2026, was filed after the mailing date of the non-final rejection. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed April 16th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 3-7, “Remarks”) that Lin fails to teach the limitations presented in amended Claim 12. It is noted that embodiments for transistors 104a, 104c, and 104d are structurally distinguished from Claim 12 due to presence of dielectric isolation structures 120a, 120c, and 120d. These dielectric isolation structures physically separate the source/drain regions 110a, 110c, and 110d from respective epitaxial regions 118a, 118c, and 118d. Since Claim 12 requires that the lower source/drain region be in contact with the upper source/drain region, these three embodiments in Lin are non-analogous and cannot be used to teach the claimed vertical stacking. Focusing on the only embodiment in which contact appears to occur between the source/drain region 110b and the epitaxial region 118b, the uppermost surface of 118b is shown to be below the uppermost surface of the surrounding substrate 102.
However, as seen in more detail below, Lin teaches that a crystallized mismatch between the epitaxial semiconductor region 118b and the source/drain regions 110b and thus imparts a beneficial strain to the source/drain regions 110b improving overall conductivity ([0044]). As a result, a new interpretation of Lin’s multiple embodiments teaches the limitations presented in amended Claim 12.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant argues (pgs. 8-11, “Remarks”) that Lin and the other cited references fail to teach the limitations presented in Claims 1 and 17. Lin states that the epitaxial semiconductor regions 118 are not doped and are described as including intrinsic semiconductor material. The office action states that it would be obvious to modify Lin to dope the epitaxial semiconductor regions. However, Lin makes it clear that the epitaxial semiconductor regions 118 are not doped and are not intended to function as a doped lower source/drain region and are instead intended to function as a neutral region and adjust a height of the source/drain region 110.
Examiner agrees that Lin teaches the epitaxial semiconductor regions 118 are not doped ([0070]) and effectively extends the height of the substrate in regions for which fewer channels will be connected to the source/drain regions ([0093]). However, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this instance, Mochizuki teaches that undoped, carbon doped, and counter doped lower epitaxial portions form electrically isolated regions which prevent shorts with channel portions and reduce parasitic leakage ([0027]). It is clear that Mochizuki teaches that any of an undoped, carbon doped, and counter doped lower epitaxial portion may be used to electrically isolate channels and may be implemented as the epitaxial semiconductor region of Lin to effectively extend the height of the substrate and cover nanosheet channels.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pg. 11, “Remarks”) that Lin does not teach the limitations presented in Claim 4. Lin does not teach that the source/drain region 110c and the epitaxial semiconductor region 118 are in contact (e.g., as required by independent claim 1). As such, the only embodiment of Lin that shows and describes the source/drain region 110c and the epitaxial semiconductor region 118 being in contact is in 104b. However, an uppermost surface of the epitaxial semiconductor region 118b is not higher than an upper surface of the first nanostructure 106.
However, as stated in the response to Claim 12 above, Lin teaches that a crystallized mismatch between the epitaxial semiconductor region 118b and the source/drain regions 110b and thus imparts a beneficial strain to the source/drain regions 110b improving overall conductivity ([0044]). The embodiment of Lin with direct contact between a source/drain region 110 and an epitaxial semiconductor region 118 is not limited specifically to that as shown in 104b. Lin also states that the different embodiments are merely examples and are not intended to be limiting ([0008]) and the particular features may be combined in any suitable manner ([0013]).
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pg. 12-13, “Remarks”) that Lin does not teach the limitations presented in Claim 9. The office actions states that the source/drain region 110a overlaps the substrate 102. However, the source/drain region 110a is entirely above, and does not overlap the substrate 102 in a horizontal direction. Rather, the dielectric isolation structure 120a is located vertically between the source/drain region 110a and the substrate 102, thus making the claimed overlap impossible.
Examiner notes that the word “overlap” is defined to mean “to extend over or past and cover a part of” (sourced from Merriam Webster for “overlap”). The word does not required direct contact or an entire coverage. Therefore, it can be said that the source/drain region 110a “overlaps” the substrate 102 as there is a part of 110a that is over at least a part of 102.
Therefore, applicant’s arguments are not persuasive.
Applicant’s amendments have overcome the 35 U.S.C. 112(a) rejections of the previous office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (2023/0028900 A1; hereinafter Lin) in view of Mochizuki et al (2019/0348403 A1; hereinafter Mochizuki).
Regarding Claim 1, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D) spaced apart from the active pattern (active pattern) in a vertical direction (Z, see fig. 1A);
a second nanosheet (middle 106a, see figs. 1A and 1D) spaced apart from the first nanosheet (bottom 106a) in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), an uppermost surface of the lower source/drain region (top of 118A) being lower (see fig. 1A) than a lower surface of the second nanosheet (bottom of middle 106a), and
the lower source/drain region being doped with a second impurity having the first conductivity type;
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region (118a), the upper source/drain region (110a) being doped with a third impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118c and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
Lin doesn’t teach the lower source/drain region being doped with a second impurity having the first conductivity type.
However, Mochizuki (fig. 10) teaches the lower source/drain region ([0042], 160) being doped with a second impurity ([0043], 160 is counter-doped to the source/drain regions 165, therefore 160 may be doped N type when 165 is doped P type) having the first conductivity type (N). Mochizuki also teaches that the counter doped regions prevent shorts and reduce leakage ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Lin to include the counter doped lower source/drain region of Mochizuki to reduce leakage.
Regarding Claim 2, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, further comprising an interlayer insulation layer ([0051]-[0052], 134, 136, see fig. 1C) in contact with each of a sidewall of the lower source/drain region (118a) and a sidewall of the upper source/drain region (110a).
Regarding Claim 3, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the uppermost surface of the lower source/drain region (top of 118a) is lower (see fig. 1A) than a lower surface of the first nanosheet (bottom of bottom 106a).
Regarding Claim 4, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the uppermost surface of the lower source/drain region (top of 118a) is higher ([0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of bottom 106c, see fig. 2J) than an upper surface of the first nanosheet (top of bottom 106a).
Regarding Claim 9, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein at least a portion of the upper source/drain region (110a) overlaps (see fig. 1C) the active pattern (active pattern) in the first horizontal direction (X).
Regarding Claim 10, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the upper source/drain region (110a) is in contact with each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a).
Regarding Claim 11, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 1, wherein the lower source/drain region (118a) is in contact ([0042], [0044], transistor 104c shows that 118c and bottom 106c may be in contact) with the first nanosheet (bottom 106a), and the upper source/drain region (110a) is in contact with the second nanosheet (middle 106a).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Mochizuki as applied to Claim 1 above, and further in view of (2023/0178600 A1; hereinafter Chuang).
Regarding Claim 5, Lin doesn’t teach the semiconductor device as claimed in claim 1, wherein the upper source/drain region includes a first portion surrounded by the lower source/drain region and a second portion on the first portion, the second portion being in contact with the second nanosheet.
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion, the second portion (second portion) being in contact with the second nanosheet ([0075], middle 108a, see fig. 5A-1). Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
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Annotated Figure 5A-2
Regarding Claim 6, Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, wherein a width in the second horizontal direction of the first portion (width of first portion in the left to right direction, see annotated fig. 5A-2) of the upper source/drain region (168a) is smaller (since the first portion is curved it has a portion that has a smaller width than the active pattern) than a width in the second horizontal direction of the active pattern ([0053], portion of substrate 102 between 116, see fig. 2K).
Regarding Claim 7, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, wherein a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is lower (Lin, bottom of 110a) than a lower surface of the first nanosheet (Lin, bottom of bottom 106a).
Regarding Claim 8, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 5, a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is between (Lin, [0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of bottom 106c, see fig. 2J) a lower surface of the first nanosheet (Lin, bottom of bottom 106a) and the lower surface of the second nanosheet (bottom of middle 106a).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable by Lin in view of another embodiment of Lin.
Regarding Claim 12, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D), a second nanosheet (middle 106a, see figs. 1A and 1D), and a third nanosheet (top most 106a, see figs. 1A and 1D) sequentially stacked on the active pattern (active pattern) in a vertical direction (Z, see fig. 1A), the first nanosheet (bottom 106a), the second nanosheet (middle 106a), and the third nanosheet (top 106a) being spaced apart from each other in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first to third nanosheets (bottom 106a, middle 106a, top 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), an uppermost surface of the lower source/drain region (top of 118A) being lower (see fig. 1A) than a lower surface of the second nanosheet (bottom of middle 106a), and the lower source/drain region (118a) not being doped with an impurity ([0070], 118a may not be doped), wherein
an uppermost surface of the lower source/drain region is higher ([0042], [0088], transistor 104c shows that the top of 118 may be higher than the top of 102) than an uppermost surface of the active pattern (active pattern);
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact with the lower source/drain region, the upper source/drain region (110a) being doped with a second impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118 and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
The first embodiment of Lin doesn’t explicitly teach an upper source/drain in contact with the lower source/drain region.
However, the second embodiment of Lin (fig. 1A) teaches an upper source/drain ([0044], 118b) in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region ([0044], 110b). Lin also teaches that this may impart a beneficial strain onto the source/drain layer and improve conductivity ([0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Lin to include the contact of the second embodiment of Lin to impart strain and improve conductivity.
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Annotated Figure 1D
Regarding Claim 13, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, further comprising an interlayer insulation layer ([0051]-[0052], 134, 136, see fig. 1C) in contact with each of a sidewall of the lower source/drain region (118a) and a sidewall of the upper source/drain region (110a).
Regarding Claim 14, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, wherein the uppermost surface of the lower source/drain region (top of 118a) is lower (see fig. 1A) than a lower surface of the first nanosheet (bottom of bottom 106a).
Regarding Claim 15, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 12, wherein the uppermost surface of the lower source/drain region (top of 118a) is higher ([0042], [0088], transistor 104c shows that the top of 118c may be higher than the top of 106a) than an upper surface of the first nanosheet (top of bottom 106a).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to Claim 12 above, and further in view of Chuang.
Regarding Claim 16, Lin doesn’t teach the semiconductor device as claimed in claim 12, wherein the upper source/drain region includes a first portion surrounded by the lower source/drain region and a second portion on the first portion, the second portion being in contact with the second nanosheet.
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion, the second portion (second portion) being in contact with the second nanosheet ([0075], middle 108a, see fig. 5A-1). Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Mochizuki and Chuang.
Regarding Claim 17, Lin (figs. 1A-1D) teaches a semiconductor device ([0017], 100), comprising:
a substrate ([0017], 102);
an active pattern (portion of 102 between adjacent 134, will be referred to as active pattern, see annotated fig. 1D) extending in a first horizontal direction (X), see fig. 1C) on the substrate (102), the active pattern (active pattern) being doped with a first impurity ([0070], substrate may be doped) having a first conductivity type ([0070], since the substrate may be doped it may have either N or P conductivity type, will be referred to as N);
a first nanosheet ([0020], bottom most 106a, see figs. 1A and 1D) spaced apart from the active pattern (active pattern) in a vertical direction (Z, see fig. 1A);
a second nanosheet (middle 106a, see figs. 1A and 1D) spaced apart from the first nanosheet (bottom 106a) in the vertical direction (Z);
a gate electrode ([0022], 108a, see fig. 1D) extending in a second horizontal direction (Y, see fig. 1B) on the active pattern (active pattern) and surrounding each of the first nanosheet (bottom 106a) and the second nanosheet (middle 106a), the second horizontal direction (Y) being different from the first horizontal direction (X);
a lower source/drain region ([0031], 118a, see fig. 1A) on the active pattern (active pattern) on at least one side of the gate electrode (108a), the lower source/drain region (118a) being in contact (see fig. 1C) with the active pattern (active pattern), and
the lower source/drain region being doped with a second impurity having the first conductivity type;
an upper source/drain region ([0023], 110a, see fig. 1A) on the lower source/drain region (118a) and in contact ([0042], [0044], transistor 104b shows that 118b and 110b may instead be in contact) with the lower source/drain region (118a), the upper source/drain region (110a) being doped with a third impurity ([0023], may be doped P type for a P type transistor) having a second conductivity type (P) that is different from the first conductivity type (N),
the upper source/drain region including a first portion surrounded by the lower source/drain region and a second portion on the first portion, and
the upper source/drain region (110a) being in contact with the second nanosheet (middle 106a); and
a gate insulation layer ([0028], 114, see fig. 1A) between ([0042], [0044], transistor 104c shows that 118c and 114 may be in contact) the gate electrode (108a) and the lower source/drain region (118a) and between the gate electrode (108a) and the upper source/drain region (110a), the gate insulation layer (114) being in contact with each of the lower source/drain region (118a) and the upper source/drain region (110a).
Lin doesn’t teach the lower source/drain region being doped with a second impurity having the first conductivity type.
However, Mochizuki (fig. 10) teaches the lower source/drain region ([0042], 160) being doped with a second impurity ([0043], 160 is counter-doped to the source/drain regions 165, therefore 160 may be doped N type when 165 is doped P type) having the first conductivity type (N). Mochizuki also teaches that the counter doped regions prevent shorts and reduce leakage ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Lin to include the counter doped lower source/drain region of Mochizuki to reduce leakage.
Lin doesn’t teach the upper source/drain region including a first portion surrounded by the lower source/drain region and a second portion on the first portion.
However, Chuang (fig. 5A-2) teaches the upper source/drain region ([0116], 168a) includes a first portion (curved portion of 168a in contact with 164a, will be referred to as first portion, see annotated fig. 5A-2) surrounded (first portion is surrounded by the curved portion of 164a) by the lower source/drain region ([0150], 158a, 164a, see fig. 5A-2) (Note: 164a may be removed as taught by Lin in Claim 1 and thus 158a may directly contact 168a) and a second portion (the rest of 168a above the first portion, will be referred to as second portion, see annotated fig. 5A-2) on the first portion. Chuang teaches that the epitaxial layers may have concave, convex, or flat surfaces according to the deposition and removal steps used in the process ([0090]) and yielding the predictable results of reducing leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lower source/drain region of Chuang for the lower source/drain of Lin, since simple substitution of lower source/drain region for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 18, Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 17, wherein a width in the second horizontal direction of the first portion (width of first portion in the left to right direction, see annotated fig. 5A-2) of the upper source/drain region (168a) is smaller (since the first portion is curved it has a portion that has a smaller width than the active pattern) than a width in the second horizontal direction of the active pattern ([0053], portion of substrate 102 between 116, see fig. 2K).
Regarding Claim 19, the combination of Lin (figs. 1A-1D) and Chuang (annotated fig. 5A-2) teaches the semiconductor device as claimed in claim 17, wherein a lowermost surface of the first portion (Chuang, bottom of first portion, see annotated fig. 5A-2) of the upper source/drain region (Chuang, 168a) is lower (Lin, bottom of 110a) than a lower surface of the first nanosheet (Lin, bottom of bottom 106a).
Regarding Claim 20, Lin (figs. 1A-1D) teaches the semiconductor device as claimed in claim 17, wherein at least a portion of the upper source/drain region (110a) overlaps (see fig. 1C) the active pattern (active pattern) in the first horizontal direction (X).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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