DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, 8, 10-12, 14-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2022/0319928 to Shen et al (hereinafter Shen).
Regarding Claim 1, Shen discloses an integrated circuit comprising:
a semiconductor device having a semiconductor region (25, Fig. 24B) extending in a first direction from a source or drain region (84, Fig. 24A), and a gate electrode (104) extending in a second direction over the semiconductor region;
a first dielectric wall (40/45/50) extending in the first direction through the gate electrode and extending in the first direction adjacent to a first side of the source or drain region;
a second dielectric wall (40/45/50) extending in the first direction through the gate electrode and extending in the first direction adjacent to a second side of the source or drain region opposite from the first side of the source or drain region; and
a dielectric liner (70A, Fig. 17A) on at least a portion of the first side of the source or drain region or the second side of the source or drain region and on at least a portion of a sidewall of the first dielectric wall and at least a portion of a sidewall of the second dielectric wall (Fig. 24A).
Regarding Claim 3, Shen discloses the integrated circuit of Claim 1, wherein the dielectric liner comprises a low-k dielectric material [0059] & [0061].
Regarding Claim 4, Shen discloses the integrated circuit of Claim 1, wherein the source or drain region does not contact any sidewall of the first dielectric wall and second dielectric wall (Fig. 24C).
Regarding Claim 5, Shen discloses the integrated circuit of Claim 1, wherein the semiconductor
region comprises a plurality of semiconductor nanoribbons (Fig. 24B).
Regarding Claim 6, Shen discloses the integrated circuit of Claim 1, wherein the first dielectric wall and the second dielectric wall each extend through an entire thickness of the gate electrode (Fig. 24C).
Regarding Claim 8, Shen discloses an electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor device having a semiconductor region (25, Fig. 24B) extending in a first direction from a first source or drain region (84, Fig. 24A) to a second source or drain region, and a gate electrode (104) extending in a second direction over the semiconductor region;
a first dielectric wall (40/45/50) extending in the first direction through the gate electrode and extending in the first direction adjacent to a first side of the first source or drain region and adjacent to a first side of the second source or drain region;
a second dielectric wall (40/45/50) extending in the first direction through the gate electrode and extending in the first direction adjacent to a second side of the first source or drain region opposite from the first side of the first source or drain region and adjacent to a second side of the second source or drain region opposite from the first side of the second source or drain region; and
a first dielectric liner (70A, Fig. 17A) on at least a portion of the first source or drain region and a second dielectric liner on at least a portion of the second source or drain region (Fig. 24A).
Regarding Claim 10, Shen discloses the electronic device of Claim 8, wherein the first and second dielectric liners comprise a low-k dielectric material [0059] & [0061].
Regarding Claim 11, Shen discloses the electronic device of Claim 8, wherein the first source or drain region and the second source or drain region do not contact any sidewall of the first dielectric wall and second dielectric wall (Fig. 24A).
Regarding Claim 12, Shen discloses the electronic device of Claim 8, wherein the first dielectric wall and the second dielectric wall each extend through an entire thickness of the gate electrode (Fig. 24C).
Regarding Claim 14, Shen discloses an integrated circuit comprising:
a first semiconductor device having a first semiconductor region (25, Fig. 24B) extending in a first direction from a first source or drain region (84, Fig. 24A), and a first gate structure (104) extending in a second direction over the first semiconductor region, the first gate structure comprising a first gate electrode (104) and a first gate dielectric (102);
a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region, the second gate structure comprising a second gate electrode and a second gate dielectric, and the second source or drain region being adjacent to the first source or drain region along the second direction (Figs. 24A-24D);
a dielectric wall (40/45/50) extending in the first direction between and contacting both the first gate electrode and the second gate electrode and extending in the first direction between the first source or drain region and the second source or drain region (Fig. 24C);
a first dielectric liner (70A) on at least a portion of the first source or drain region and on at least a portion of a first sidewall of the dielectric wall; and
a second dielectric liner (70A) on at least a portion of the second source or drain region and on at least a portion of a second sidewall of the dielectric wall.
Regarding Claim 15, Shen discloses the integrated circuit of Claim 14, further comprising a first conductive contact on a top surface of the first source or drain region and a second conductive contact on a top surface of the second source or drain region [0077].
Regarding Claim 17, Shen discloses the integrated circuit of Claim 14, wherein the first and second dielectric liners comprise a low-k dielectric material [0059] & [0061].
Regarding Claim 18, Shen discloses the integrated circuit of Claim 14, wherein the first source or drain region does not contact any portion of the first sidewall of the dielectric wall and/or the second source or drain region does not contact any portion of the second sidewall of the dielectric wall (Fig. 24A).
Regarding Claim 19, Shen discloses the integrated circuit of Claim 14, wherein the dielectric wall extends through an entire thickness of the first gate electrode and second gate electrode (Fig. 24C).
Allowable Subject Matter
Claims 2, 7, 9, 13, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2, 9 and 16 require the dielectric liner be also on at least a portion of a top surface of the source or drain region. Claims 7, 13 and 20 requires one or more voids be within the dielectric liner adjacent to the first or second side of the source or drain region. A search of other, relevant references does not show the limitations claimed by Applicant to be obvious or anticipated.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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