Prosecution Insights
Last updated: August 17, 2026
Application No. 18/126,127

CHIRAL SPIN-CURRENT SUPPLY STRUCTURE FOR MTJ-BASED MEMORY

Non-Final OA §103
Filed
Mar 24, 2023
Examiner
KARIMY, TIMOR
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
854 granted / 1039 resolved
+14.2% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1084
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
20.1%
-19.9% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1039 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12 & 14-19 in the reply filed on 05/14/2026 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4, 6, 8-10 & 15-19 are3 rejected under 35 U.S.C. 103 as being unpatentable over CHIA (US Pub. 2021/0159395) in view of Ou et al. (US Pub. 2018/0301266). Regarding claim 1, CHIA teaches a memory structure comprising: a structure 600 comprising an inner core (632, 642, Fig. 11) or (120,130 & 140, Fig. 1) composed of a spin- collector material (e.g. para [0035]), a spin-conducting insulating layer 671 surrounding the inner core (632, 642), and a charge- current conducting spin-orbit spin-current generating layer (621, 622) surrounding the spin-conducting insulating layer 671 (Fig. 1-12); a magnetic tunnel junction (MTJ) structure having a magnetic free layer 20 forming an interface with a surface of the inner core (632, 642, see Fig. 11-12); and a charge current connection 610/611 connecting the inner core to the charge-current conducting spin-orbit spin-current generating layer (621, 622, Fig. 11-12). CHIA is silent on wherein the structure is a chiral spin-current supply structure. However, Ou teaches in Para [0036 & claim 18) wherein a memory structure comprises chiral spin-current supply structure. This has the advantages of high spin polarization and superior interface integration. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of CHIA with the Chiral-spin current supply structure, as taught by Ou, so as to obtain an improved semiconductor device. Regarding claim 2, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the spin-collector material is composed of a metal or metal alloy having a spin-conductance and spin-diffusion length comparable to high-quality copper (Para [0035], Pt or Ni or their alloy is understood to have a spin-conductance and spin-diffusion length comparable to high-quality copper). Regarding claim 4, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the spin-conducting insulating layer 671 is composed of a magnetic insulator (Fig. 1-12 & Para [0063]). Regarding claim 6, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the charge-current conducting spin-orbit spin-current generating layer (621, 622) comprises a spin-orbit torque (SOT) channel material (Fig. 11-12 and associated text). Regarding claim 8, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the MTJ structure comprises, from bottom to top, the magnetic free layer 120/620, a magnetic tunnel barrier layer 130/630, a magnetic reference layer (140 or 640), and an electrode layer (110/610, Fig. 1-12). Regarding claim 9, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the MTJ structure comprises, from bottom to top, an electrode layer 611, a magnetic reference layer 640, a magnetic tunnel barrier layer 630, and the magnetic free layer 620 (Fig. 11-12). Regarding claim 10, the combination of CHIA and Ou teaches the memory structure of Claim 1, further comprising an electrically conductive structure 611 directly contacting a horizontal surface of the charge-current conducting spin-orbit spin-current generating layer 671/672 (Fig. 11-12). Regarding claim 15, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the charge-current conducting spin-orbit spin-current generating layer 621/622 supports chiral charge current flow surrounding the inner core so as to generate a spin-current with spin polarization substantially out of the plane of the inner core's horizontal surface that contacts the MTJ structure (Fig. 11-12: because the combination of prior art teaches the structural and material composition features; therefore, the device is capable of said functionality). Regarding claim 16, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the charge current connection between the inner core (632, 642) and the charge-current conducting spin-orbit spin-current generating layer (621,622) enables chiral charge current flow in the charge-current conducting spin-orbit spin-current generating layer (Fig. 11-12: because the combination of prior art teaches the structural and material composition features; therefore, the device is capable of said functionality). Regarding claim 17, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the charge current connection between the inner core and the charge-current conducting spin-orbit spin-current generating layer is a direct electrical contact structure (Fig. 11-12). Regarding claim 18, the combination of CHIA and Ou teaches the memory structure of Claim 1, wherein the charge current connection between the inner core and the charge-current conducting spin-orbit spin-current generating layer is provided by a controlled amount of leakage current across the spin-conducting insulating layer from the inner core to the charge-current conducting spin-orbit spin-current generating layer, allowing an accumulation of current flow in the charge-current conducting spin-orbit spin- current generating layer to form a chiral charge current (Fig. 1-12: because the combination of prior art teaches the structural and material composition features; therefore, the device is capable of said functionality). Regarding claim 19, the combination of CHIA and Ou teaches the memory structure of Claim 1, the charge-current conducting spin-orbit spin- current generating layer (621, 622) is electrically connected to a first terminal, and the MTJ structure is electrically connected to a second terminal (both electrodes 610 and 611 are understood to be connected to two terminals, Fig. 11-12). Allowable Subject Matter Claims 3, 5, 7, 11-12 & 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOR KARIMY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Mar 24, 2023
Application Filed
Jun 10, 2024
Response after Non-Final Action
Jul 20, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY DEVICE STRUCTURE AND FABRICATION METHOD
3y 7m to grant Granted Aug 04, 2026
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Patent 12690198
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Patent 12677426
SEMICONDUCTOR DEVICE STRUCTURE
2y 10m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.5%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1039 resolved cases by this examiner. Grant probability derived from career allowance rate.

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