DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/126,128 application filed on 03/24/2023. Claims 1-20 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 03/24/2023 and 02/21/2024, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1-4, 6 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US PG Pub No. 2014/0013293) in view of Srinivasan et al. (US Patent No. 11,442,108).
7. With respect to independent claim 1, Hsu teaches:
An operating method of an electronic device including at least one processor, which simulates a design of an integrated circuit (simulation of power domain structure of integrated circuit, para 14), the method comprising:
obtaining, by the at least one processor, a power domain structure of the integrated circuit (see various power domains of IC, Abstract; see power map/structure, Abstract; see power structure, para 11);
obtaining, by the at least one processor, current isolation values of a plurality of ports of the integrated circuit from the power domain structure of the integrated circuit and an unified power format (UPF) of the integrated circuit (see current values of simulation results for power switch cells, isolation cells, para 14, 38-40, 49; see isolation cells, power structure format specified in UPF format, para 8, 32);
obtaining, by the at least one processor, reference isolation values of the plurality of ports of the integrated circuit (signals of power specification, para 34; values of power specification, para 35; power specification isolation cells, para 43);
obtaining, by the at least one processor, reset values of the plurality of ports of the integrated circuit (see reset values as shown in Fig 5; see ports, para 7); and
checking, by the at least one processor, isolation errors of the plurality of ports of the integrated circuit based on the current isolation values, the reference isolation values, and the reset values (checking to identify mismatches or errors between power specification values of isolation elements/cells and the current isolation values of the circuit design and considering reset functions, para 34, 47, 55).
Hsu appears to be silent regarding:
the power domain structure is obtained from an RTL model.
However, Srinivasan teaches:
the power domain structure is obtained from an RTL model (see power domain structure specified in RTL, Col 15, lines 55-65).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated the RTL model of the power domain structure disclosed in Srinivasan into the invention of Hsu for at least the following reason(s): Srinivasan discloses that it is well known to have power domain descriptions of an integrated circuit formatted in RTL, including RTL code, gate-level simulations, and isolation cell code for power domain structures, which would provide an advantage to Hsu by providing the power domain structure of Hsu in a readily accepted format such as RTL, as taught by Srinivasan.
8. With respect to claim 2, Hsu teaches:
The method of claim 1, wherein the plurality of ports of the integrated circuit comprise a port for transferring a signal between a first power domain circuit and a second power domain circuit of the power domain structure (level shifter connections between two power domains, para 47; signals between power domains, para 4).
9. With respect to claim 3, Hsu teaches:
The method of claim 1, wherein the plurality of ports of the integrated circuit comprise a port for transferring a signal between a power domain circuit of the power domain structure and a bus (ports to ports at power interface/bus, para 7).
10. With respect to claim 4, Hsu teaches:
The method of claim 1, wherein the obtaining the reference isolation values of the plurality of ports of the integrated circuit comprises: obtaining the reference isolation values from specifications of power domains of the power domain structure (signals of power specification, para 34; reference values of power specification, para 35; power specification isolation cells, para 43).
11. With respect to claim 6, Hsu teaches:
The method of claim 1, wherein the checking the isolation errors of the plurality of ports of the integrated circuit comprises: based on an existence of a reference isolation value corresponding to a first port, from among the plurality of ports of the integrated circuit, comparing the reference isolation value of the first port with a current isolation value of the first port (if isolation control is not missing, then mismatch check for errors at ports for isolation values is performed, para 47).
12. With respect to independent claim 17, Hsu teaches:
An operating method of an electronic device including at least one processor, which simulates a design of an integrated circuit (simulation of power domain structure of integrated circuit, para 14), the method comprising:
obtaining, by the at least one processor, a power domain structure of the integrated circuit (see various power domains of IC, Abstract; see power map/structure, Abstract; see power structure, para 11);
obtaining, by the at least one processor, current isolation values of a plurality of ports of the integrated circuit from the power domain structure of the integrated circuit and an unified power format (UPF) of the integrated circuit (see current values of simulation results for power switch cells, isolation cells, para 14, 38-40, 49; see isolation cells, power structure format specified in UPF format, para 8, 32);
obtaining, by the at least one processor, reference isolation values of the plurality of ports of the integrated circuit (signals of power specification, para 34; values of power specification, para 35; power specification isolation cells, para 43); and
checking, by the at least one processor, isolation errors of the plurality of ports of the integrated circuit based on a difference between the current isolation values and the reference isolation values (checking to identify mismatches or errors between power specification values of isolation elements/cells and the current isolation values of the circuit design and considering reset functions, para 34, 47, 55).
Hsu appears to be silent regarding:
the power domain structure is obtained from an RTL model.
However, Srinivasan teaches:
the power domain structure is obtained from an RTL model (see power domain structure specified in RTL, Col 15, lines 55-65).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated the RTL model of the power domain structure disclosed in Srinivasan into the invention of Hsu for at least the following reason(s): Srinivasan discloses that it is well known to have power domain descriptions of an integrated circuit formatted in RTL, including RTL code, gate-level simulations, and isolation cell code for power domain structures, which would provide an advantage to Hsu by providing the power domain structure of Hsu in a readily accepted format such as RTL, as taught by Srinivasan.
13. With respect to claim 18, Hsu teaches:
wherein the obtaining the reference isolation values of the plurality of ports of the integrated circuit includes: obtaining the reference isolation values from specifications of power domains of the power domain structure (signals of power specification, para 34; values of power specification, para 35; power specification isolation cells, para 43).
14. With respect to independent claim 19, Hsu teaches:
An operating method of an electronic device including at least one processor, which simulates a design of an integrated circuit (simulation of power domain structure of integrated circuit, para 14), the method comprising:
obtaining, by the at least one processor, a power domain structure (see various power domains of IC, Abstract; see power map/structure, Abstract; see power structure, para 11);
obtaining, by the at least one processor, current isolation values of a plurality of ports of the integrated circuit from the power domain structure of the integrated circuit and an unified power format (UPF) of the integrated circuit (see current values of simulation results for power switch cells, isolation cells, para 14, 38-40, 49; see isolation cells, power structure format specified in UPF format, para 8, 32);
obtaining, by the at least one processor, reset values of the plurality of ports of the integrated circuit (see reset values as shown in Fig 5; see ports, para 7); and
checking, by the at least one processor, isolation errors of the plurality of ports of the integrated circuit based on a difference between the current isolation values and the reset values (checking to identify mismatches or errors between power specification values of isolation elements/cells and the current isolation values of the circuit design and considering reset functions, para 34, 47, 55).
Hsu appears to be silent regarding:
the power domain structure is obtained from an RTL model.
However, Srinivasan teaches:
the power domain structure is obtained from an RTL model (see power domain structure specified in RTL, Col 15, lines 55-65).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated the RTL model of the power domain structure disclosed in Srinivasan into the invention of Hsu for at least the following reason(s): Srinivasan discloses that it is well known to have power domain descriptions of an integrated circuit formatted in RTL, including RTL code, gate-level simulations, and isolation cell code for power domain structures, which would provide an advantage to Hsu by providing the power domain structure of Hsu in a readily accepted format such as RTL, as taught by Srinivasan.
Allowable Subject Matter
15. Claims 5, 7-16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
16. With respect to claims 5 and 20, the prior art made of record fails to teach the combination of steps recited in claims 5 and 20, including the following particular combination of steps as recited in claim 5 and similarly recited in claim 20, as follows:
wherein the obtaining the reset values of the plurality of ports of the integrated circuit includes: obtaining the reset values of the plurality of ports of the integrated circuit from a result of a non-power-aware simulation of the integrated circuit.
17. With respect to claims 7, the prior art made of record fails to teach the combination of steps recited in claim 7, including the following particular combination of steps as recited in claim 7, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reference isolation value of the first port being identical to the current isolation value of the first port, confirming the current isolation value of the first port.
18. With respect to claims 8, the prior art made of record fails to teach the combination of steps recited in claim 8, including the following particular combination of steps as recited in claim 8, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reference isolation value of the first port being different from the current isolation value of the first port, correcting the current isolation value of the first port.
19. With respect to claims 9, the prior art made of record fails to teach the combination of steps recited in claim 9, including the following particular combination of steps as recited in claim 9, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on a non-existence of the reference isolation value corresponding to a first port from among the plurality of ports of the integrated circuit, comparing a reset value of the first port with a current isolation value of the first port.
20. With respect to claims 10, the prior art made of record fails to teach the combination of steps recited in claim 10, including the following particular combination of steps as recited in claim 10, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reference isolation value of the first port being identical to the current isolation value of the first port, displaying that a correction of the current isolation value of the first port is not needed.
21. With respect to claims 11, the prior art made of record fails to teach the combination of steps recited in claim 11, including the following particular combination of steps as recited in claim 11, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reference isolation value of the first port being different from the current isolation value of the first port, displaying that a correction of the current isolation value of the first port is necessary.
22. With respect to claims 12, the prior art made of record fails to teach the combination of steps recited in claim 12, including the following particular combination of steps as recited in claim 12, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reference isolation value of the first port being identical to the current isolation value of the first port, increasing a score of the first port.
23. With respect to claims 13, the prior art made of record fails to teach the combination of steps recited in claim 13, including the following particular combination of steps as recited in claim 13, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: comparing a reset value of a first port from among the plurality of ports of the integrated circuit with a current isolation value of the first port.
24. With respect to claims 14, the prior art made of record fails to teach the combination of steps recited in claim 14, including the following particular combination of steps as recited in claim 14, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: based on the reset value of the first port being identical to the current isolation value of the first port, increasing a score of the first port.
25. With respect to claims 15, the prior art made of record fails to teach the combination of steps recited in claim 15, including the following particular combination of steps as recited in claim 15, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: displaying identifiers of the plurality of ports of the integrated circuit, the current isolation values, whether the current isolation values are identical to the reference isolation values, and whether the current isolation values are identical to the reset values.
26. With respect to claims 16, the prior art made of record fails to teach the combination of steps recited in claim 16, including the following particular combination of steps as recited in claim 16, as follows:
wherein the checking the isolation errors of the plurality of ports of the integrated circuit further comprises: displaying the reference isolation values and the reset values.
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851