243The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (2012/0187410) in view of Shih et al. (11,264,391).
Regarding claims 1 and 21, Yamazaki et al. teach in figure 6 and related text a semiconductor memory device, comprising:
a substrate (402, FIG. 6, [0123]);
a buried dielectric layer (146/130/143a/143b, noting the transistor in FIG. 6 is the same transistor described in FIG. 1, [0122]) on the substrate (402) and providing a first recess that extends in a first direction (vertical direction, FIG. 6);
a word line (the bottom part of element 148a, FIG. 1, [0055]) disposed in the first recess of the buried dielectric layer, extending in the first direction, and spaced apart in a vertical direction from the substrate;
first (142a, FIG. 6, [0048]) and second source/drain patterns (142b, FIG. 6,
[0048]) on opposite sides of the word line (148a);
a channel pattern (144, FIG. 1, [0037]) between the word line (148a) and the buried dielectric layer (130/143a/143b) in the first recess, the channel pattern (144) being connected to the first and second source/drain patterns (142a/142b); and
a bit line (156 FIG. 6, [0125]) electrically connected to the second source/drain
pattern (142b) and extending in a second direction (horizontal, FIG. 6) that intersects
the first direction (vertical),
wherein the channel pattern (144) includes vertical parts and a horizontal part (annotated FIG. 6) connected to each other,
wherein the vertical parts (annotated FIG. 6) are on opposite lateral surfaces of the word line (148a), and extend in the vertical direction
wherein the horizontal part is below the word line (148a),
wherein, in the vertical direction, a top surface of the buried dielectric layer is higher than a top surface of the word line, and
wherein the first and second directions are parallel to an upper surface of the substrate and the vertical direction is perpendicular to each of the first and second directions.
Regarding the claimed limitation “wherein in the vertical direction, a top surface of the buried dielectric layer is higher than a top surface of the word line”, Yamazaki et al. teach the above limitation for the following reason. The claim requires that the word line is buried in the first recess of the dielectric layer. Thus, only the vertical narrow portion of element 148a is considered as the claimed word line wherein its top surface is aligned with the top surface of element 144. The top surface of said buried word line portion is clearly located below a top surface of the buried dielectric layer 146/130/143a/143b.
In the alternative, Shih et al. teach in figure 9 and related text a word line 150 disposed in the first recess, comprising two materials 151, 152, and wherein in the vertical direction, a top surface of the substrate 100 is higher than a top surface of the word line 150.
Yamazaki et al. and Shih et al. are analogous art because they are directed to word lines and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamazaki et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the word line comprising two materials, such that one material is located in the vertical narrow portion, and wherein in the vertical direction, a top surface of the dielectric layer is higher than a top surface of the buried word line, as taught by Shih et al., in Yamazaki et al.’s device, in order to provide better protection to the word line.
Regarding claim 2, Yamazaki teaches the semiconductor memory device of
claim 1, wherein top surfaces of the vertical parts (annotated FIG. 6) of the channel
pattern (144) are in contact with the first and second source/drain patterns (142a/142b).
Regarding claim 3, Yamazaki teaches the semiconductor memory device of
claim 1, further comprising: a gate dielectric pattern (146, FIG. 1, [0051]) between the
word line (148a) and the channel pattern (144).
Regarding claim 4, Yamazaki teaches the semiconductor memory device of
claim 1, further comprising: a gate capping pattern (149, FIG. 1, [0058]) on the word line
(148a), wherein a top surface of the gate capping pattern (149) is coplanar with a top
surface of the buried dielectric layer (130/143a/143b; noting the direction in which the
top surfaces are coplanar is not specified, and two surfaces are coplanar if there exists
a geometrical plane that contains them both; see annotated FIG. 1 below).
Regarding claim 5, Yamazaki teaches the semiconductor memory device of
claim 1, wherein the first and second source/drain patterns (142a/142b) are on the
buried dielectric layer (130/143a/143b).
Regarding the claimed limitations of forming word line of one material these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of a word line in one process does not produce a structure which is different from a structure which is formed by using two processes.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Claims 12-14 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (2012/0187410) in view of Shih et al. (11,264,391).
Regarding claim 12, Yamazaki et al. teach in figure 6 and related text a semiconductor memory device, comprising:
a substrate (402, FIG. 6, [0123]) that includes a cell array region (region of 251,
FIG. 5B, [0117], also refer to annotated FIG. 6) and a peripheral circuit region (region of 253, FIG. 5B, [0117]);
a buried dielectric layer (403/420/422/425/130. see annotated FIG. 6,
[0124]/[0039], noting the transistor in FIG. 6 is the same transistor described in FIG. 1,[0122]) on the substrate (402) and including first recesses that extend in a first direction (vertical direction in FIG. 6) on the cell array region (region of 521, FIG. 5B);
word lines (148a, FIG. 1, [0055]) disposed in corresponding first recesses
extending in the first direction and spaced apart in a vertical direction from the substrate;
channel patterns (144, FIG. 1, [0037]) between the buried dielectric layer
(403/420/422/425/130) and the word lines (148a);
first (142a, FIG. 6, [0048]) and second source/drain patterns (142b, FIG. 6,
[0048]) on opposite sides of each of the word lines (148a);
bit lines (156 FIG. 6, [0125]) that extend in a second direction (horizontal, FIG. 6)
intersecting the first direction (vertical) on the first and second source/drain patterns (142a/142b);
bit-line contacts 430 that connect the second source/drain patterns (142b) to the bit lines (156);
data storage patterns (254, FIG. 5A); and
a peripheral transistor (450, FIG. 6, [0123]) on the peripheral circuit region and on the buried dielectric layer (403/420/422/425/130) wherein the channel patterns (144) are in contact with the first and second source/drain patterns,
wherein cell transistors of the cell array region 250 and the peripheral transistor 450 of the peripheral circuit region are entirely spaced apart from each other in the second direction.
wherein the peripheral transistor 450 includes:
a channel layer on the buried dielectric layer; and
a gate pattern and peripheral source/drain patterns on the channel layer,
wherein a thickness of each of the channel patterns is the same as a thickness of the channel layer (since they are both the same element), and
wherein the first and second directions are parallel to an upper surface of the substrate, and
the vertical direction is perpendicular to each of the first and second directions.
Yamazaki does not explicitly teach the data storage patterns (254) are on the first
source/drain patterns (142a); and storage contacts that connect the data storage
patterns (254) to the first source/drain patterns (142a).
Yoon teaches in FIG. 42 and related text, data storage patterns (CAS, [0131]) are on first source/drain patterns (SD2); and storage contacts (210, [0130]) that connect the data storage patterns (CAS) to the first source/drain patterns (SD2).
Yamazaki and Yoon are analogous art to the claimed invention because they are
directed to semiconductor memory devices and one of ordinary skill in the art would
have had a reasonable expectation of success to modify Yamazaki in view Yoon
because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamazaki such that the data storage patterns are on the first source/drain patterns; and storage contacts connect the
data storage patterns to the first source/drain patterns, as taught by Yoon, in order to
reduce the overall footprint of the memory device, and to provide electrical contact
between the first source/drain pattern and the data storage pattern.
Regarding claim 13, Yamazaki as modified by Yoon teaches the semiconductor
memory device of claim 12. Yamazaki further teaches wherein the peripheral source/drain patterns (406/408) are on opposite sides of the gate pattern (412).
Regarding claim 14, Yamazaki as modified by Yoon teaches the semiconductor
memory device of claim 12. Yamazaki further teaches comprising: gate dielectric
patterns (146, FIG. 1, [0051]) between the channel patterns (144) and the word lines
(148a); and gate capping patterns (149, FIG. 1, [0058]) on the word lines (148a), wherein in the vertical direction a top surface of each of the gate capping patterns (149) is coplanar with a top surface of the buried dielectric layer (403/420/422/425/130; noting the direction in which the top surfaces are coplanar is not specified, and two surfaces are coplanar if there exists a geometrical plane that contains them both.
Regarding claim 22, Yamazaki et al. teach in figure 6 and related text the channel patterns and the channel layer are simultaneously formed.
Regarding the claimed limitations of “the channel patterns and the channel layer are simultaneously formed” these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. The formation of the channel patterns and the channel layer in one process does not produce a structure which is different from a structure which is formed by using two processes.
Regarding claim 23, Yamazaki et al. teach in figure 6 and related text that the channel patterns include the same material as the channel layer (since they are the same element).
Response to Arguments
1. Applicants argue that Yamazaki does not teach that the cell transistors of the cell array region 250 and the peripheral transistor 450 of the peripheral circuit region are entirely spaced apart from each other in the second direction.
1. Figure 6 of Yamazaki clearly depicts that the cell transistors of the cell array region 250 and the peripheral transistor 450 of the peripheral circuit region are entirely spaced apart from each other in any direction.
2. Applicants argue that “Yamazaki does not show that a thickness of the oxide semiconductor layer 144 (which the Examiner interpreted as the channel pattern) is the same as a thickness of a channel formation region 404 (which the Examiner interpreted as the claimed channel layer)”.
2. The examiner cannot find that the previous examiner states that element 144 is interpreted as the channel pattern and that the channel formation region 404 is interpreted as the claimed channel layer. In any event, the element channel pattern and the element channel formation region refer to the same element (channel) wherein “channel pattern”.
3. The rest of applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
8/15/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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