DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions - Confirmation
Applicant’s confirmation of election without traverse of Group I: Claims 1, 3-13 and 15-16 in the reply filed on 10/10/2025 is acknowledged. It is noted that in the restriction requirement, Group I was listed as claims 1-16, but claims 2 and 14 have now been cancelled (see applicant’s claims and response of 10/10/2025).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4 and 6-9, 13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan (US 20150115451) of prior record, hereinafter Viswanathan, in view of Molla (US 20190148138) of prior record, hereinafter Molla.
Regarding claim 1, Viswanathan (refer to Figure 5 described in para 36; also see variations shown in figure 6 and 7 described respectively in para 37 and 38) teaches a substrate (comprising 510 of Figure 5, para 36; alternatively 610 of Figure 6, OR 710 of Figure 7), comprising:
a heat slug (540 of Figure 5, described as “copper slug 540” in para 36; alternatively 640 and/or 645 of Figure 6, or 740 of Figure 7) disposed in a cavity (cavity in 510 corresponding to 515 of Figure 5, describes a “large via 515” in para 36; alternatively 615 of Figure 6, OR 715 of Figure 7) in the substrate, the heat slug formed of a conductive material (i.e. copper – see para 36); and
an engineered filler material (530 of Figure 5, such as nano-silver paste – see para 36; alternatively 630 of Figure 6, OR 730 of Figure 7) disposed in the cavity over the heat slug, the engineered filler material comprising a thermally and electrically conductive particle material (such as nano-silver paste described in para 36);
The embodiments of Figures 5-7 of Viswanathan do not show “an electronic device attached to the substrate over the heat slug by a die attach material”. However, Viswanathan discloses (see Figure 3) that an electronic device (340, para 27) may be attached to a substrate with a heat slug (320, para 27) providing a heat transfer dissipation path (para 27), and that die attach materials like “silver die attach” (para 28) are known. Further, Viswanathan does not teach the substrate further comprises “a routing line disposed in the substrate and electrically connected to the electronic device through the die attach material, the heat slug and the engineered filler material so as to propagate a radio frequency (RF) signal”. Molla teaches a similar substrate (26, para 38 – see Figure 1) comprising a heat slug (62, describes in para 44 as “thermal conduit member 62", and para 34 discloses “thermal conduit member” can be a “slug”), further teaching that heat dissipating structure (22, para 42), which includes heat slug (62, see para 44, 1st sentence), additionally utilized to “electrically interconnect” (para 54) to conductors such as a routing line (48, described as “wiring layer 48” in para 54, see Figure 1) disposed in the substrate (para 54); and also teaches that in RF applications, the heat dissipation structure may be leveraged to provide a relatively direct, low resistance electrical interconnection between a ground pad of a heat-generating microelectronic component, and a ground layer of substrate to which the electronic device is mounted (see para 31 of Molla) .
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan to further include “an electronic device attached to the substrate over the heat slug by a die attach material” wherein the substrate further comprises “a routing line disposed in the substrate and electrically connected to the electronic device through the die attach material, the heat slug and the engineered filler material so as to propagate a radio frequency (RF) signal”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of using a large, highly conductive conductor such as the heat slug to not only enhance heat transfer, but also provide a low electrical resistance path for grounding of RF components (para 31 and 54 of Molla).
Regarding claim 3, Viswanathan teaches the substrate of claim 1, further comprising a via structure, the via structure (via structure corresponding to 515 of Figure 5 described as “large via 515” in para 36; alternatively, 615 of Figure 6 or 715 of Figure 7) comprising: a via formed in the substrate (i.e. in 510); a conductive material (520 of Figure 5; alternatively, 620 of Figure 6 or 720 of Figure 7 – see para 37 which describes 620 may be “gold, silver or copper”) disposed over a first side and a second side of the via; and the engineered filler material (530 or 630 or 730) disposed in the via between (best seen in any one of Figures 5-7) the first and the second sides of the via.
Regarding claim 4, Viswanathan teaches the substrate of claim 1, further comprising a via structure (via structure corresponding to 515 of Figure 5 described as “large via 515” in para 36; alternatively, 615 of Figure 6 or 715 of Figure 7), the via structure comprising: a via formed in the substrate (i.e. in 510; or alternatively in 610 of Figure 6, OR 710 of Figure 7); and a conductive material (520 of Figure 5; alternatively, 620 of Figure 6 or 720 of Figure 7 – see para 37 which describes 620 may be “gold, silver or copper”) disposed in the via (best seen in any one of Figures 5-7).
Regarding claim 6, Viswanathan teaches the substrate of claim 1, but does not teach further comprising “an outer conductive layer disposed over a surface of the substrate; and a mask layer disposed over a portion of the outer conductive layer”. Molla (US 20190148138) teaches a similar substrate (26, para 38 – see Figure 1) comprising a heat slug (62, describes in para 44 as “thermal conduit member 62", and para 34 discloses “thermal conduit member” can be a “slug”), further teaching that disposing a mask (76, described as "patterned solder mask layer 76" in para 51) over a portion of an outer conductive layer (46, described as “first patterned metal layer 46” in para 40; see figure 1) of the substrate (26) is known in the art (para 51), further disclosing that "A patterned solder mask layer 76 is further formed over PCB frontside 38 between microelectronic component 24 and substrate 26. Solder mask layer 76 is patterned to provide the desired electrical isolation between solder contacts 68, 70, 72, 74" (see para 51). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan to further comprise “an outer conductive layer disposed over a surface of the substrate; and a mask layer disposed over a portion of the outer conductive layer”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of providing an outer conductive layer to connect a microelectronic component to the substrate by solder contacts, employing a patterned solder mask layer to provide the desired electrical isolation between the solder contacts (see para 51 of Molla).
Regarding claim 7, Viswanathan teaches the substrate of claim 1, wherein the cavity (cavity in 510 corresponding to 515 of Figure 5, describes a “large via 515” in para 36; alternatively 615 of Figure 6, OR 715 of Figure 7) extends through the substrate from a top surface of the substrate (510) to a bottom surface of the substrate (best seen in any one of Figures 5-7).
Regarding claim 8, Viswanathan teaches the substrate of claim 1, wherein the heat slug is included in a heat slug array (see Figure 6, which shows an array of 2x1 heat slugs comprising 640 and 645; see para 37), the heat slug array comprised of more than one heat slugs, but does not teach that the “more than one slugs” is “multiple heat slugs” (noting that multiple sometimes refers to more than 2). It would have been obvious to one of ordinary skill in the art to use an array of more than two heat slugs (i.e. multiple heat slugs) that are substantially the same in a similar array as claimed, because such ‘structure, is considered to be a duplication of parts that has no patentable significance unless a new unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), MPEP 2144.04.
Regarding claim 9, Viswanathan (refer to Figure 5 described in para 36; also see variations shown in figure 6 and 7 described respectively in para 37 and 38) integrated circuit (IC) package, comprising:
a cavity cavity in 510 corresponding to 515 of Figure 5, describes a “large via 515” in para 36; alternatively 615 of Figure 6, OR 715 of Figure 7) formed in a substrate (comprising 510 of Figure 5, para 36; alternatively 610 of Figure 6, OR 710 of Figure 7);
a heat slug (540 of Figure 5, described as “copper slug 540” in para 36; alternatively 640 and/or 645 of Figure 6, or 740 of Figure 7) disposed in the cavity, the heat slug formed of a thermally and electrically conductive material (i.e. copper – see para 36);
an engineered filler material (530 of Figure 5, such as nano-silver paste – see para 36; alternatively 630 of Figure 6, OR 730 of Figure 7) disposed in the cavity over the heat slug (540), the engineered filler material comprising a thermally and electrically conductive particle material (such as nano-silver paste described in para 36); and
the heat slug and the engineered filler material providing a heat transfer dissipation path (as they are made of thermally conductive materials).
The embodiments of Figures 5-7 of Viswanathan do not show “an electronic device attached by way of a die attach material” so that said heat transfer dissipation path is “for the electronic device”. However, Viswanathan discloses (see Figure 3) that an electronic device (340, para 27) may be attached to a substrate with a heat slug (320, para 27) providing a heat transfer dissipation path (para 27), and that die attach materials like “silver die attach” (para 28) are known. Further, Viswanathan does not teach the substrate further comprises “a routing line disposed in the substrate and electrically connected to the electronic device through the die attach material, the heat slug and the engineered filler material so as to propagate a radio frequency (RF) signal”. Molla teaches a similar substrate (26, para 38 – see Figure 1) comprising a heat slug (62, describes in para 44 as “thermal conduit member 62", and para 34 discloses “thermal conduit member” can be a “slug”), further teaching that heat dissipating structure (22, para 42), which includes heat slug (62, see para 44, 1st sentence), additionally utilized to “electrically interconnect” (para 54) to conductors such as a routing line (48, described as “wiring layer 48” in para 54, see Figure 1) disposed in the substrate (para 54); and also teaches that in RF applications, the heat dissipation structure may be leveraged to provide a relatively direct, low resistance electrical interconnection between a ground pad of a heat-generating microelectronic component, and a ground layer of substrate to which the electronic device is mounted (see para 31 of Molla) .
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan to further include “an electronic device attached by way of a die attach material” so that said heat transfer dissipation path is “for the electronic device” and wherein the substrate further comprises “a routing line disposed in the substrate and electrically connected to the electronic device through the die attach material, the heat slug and the engineered filler material so as to propagate a radio frequency (RF) signal”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of using a large, highly conductive conductor such as the heat slug to not only enhance heat transfer, but also provide a low electrical resistance path for grounding of RF components (para 31 and 54 of Molla).
Regarding claim 13, Viswanathan teaches the IC package of claim 9, but in embodiments of Figures 5-7 it does not show details such as “further comprising a wire bond attached to the electronic device and attached to an outer conductive layer that is disposed over a surface of the substrate”. However, Figure 4 of Viswanathan shows an IC package with a similar substrate (410 of Figure 4 or 310 of Figure 3, para 33), further comprising a wire bond (370, para 29) attached to an electronic device and attached to an outer conductive layer that is disposed over a surface of the substrate (370, para 29, especially 1st sentence). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan so that it further comprises “a wire bond attached to the electronic device and attached to an outer conductive layer that is disposed over a surface of the substrate”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of using using a known interconnection method such as wire bonding for which equipment is readily available to connect a “power device die 340” of Figure 3 (see para 27 of Viswanathan) to metallization on the substrate, thus creating an electronic assembly that can effectively cool the heat producing power device die for improved device reliability.
Regarding claims 15 and 16, Viswanathan teaches the IC package of claim 9, but in embodiments of Figures 5-7 it does not show details of the IC package sealing enclosure; i.e. does not teach that the IC package enclosure comprises “a lid attached to the substrate, the substrate and the lid defining an air space therebetween with the electronic device positioned within the air space” (as recited in claim 15); OR that the IC package enclosure comprises (as recited in claim 16) “an overmolded enclosure disposed over the substrate and the electronic device”. However, Viswanathan discloses that the above variations of IC package sealing enclosures are known in the art, showing (in Figure 1) that IC package enclosure or electronic device enclosure may comprise a lid (160, para 17) attached to a substrate (110, para 17), the substrate and the lid defining an air space (170, described as “cavity 170” in para 17) therebetween with the electronic device (150) positioned within the air space (best seen in Figure 1); or alternatively, IC package enclosure or electronic device enclosure may comprise a molding encapsulant (390, see Figure 3 and para 30) forming an enclosure disposed over a substrate (310 of Figure 3, para 26) and an electronic device (340 of Figure 3, para 27). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan so that the IC package enclosure comprises “a lid attached to the substrate, the substrate and the lid defining an air space therebetween with the electronic device positioned within the air space” (as recited in claim 15); OR that the IC package enclosure comprises (as recited in claim 16) “an overmolded enclosure disposed over the substrate and the electronic device”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of using the lid or the molding encapsulant to protect the components within the IC package (para 31) from external elements.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan and Molla, as applied to claim 1 above, further in view of Lin (US 2019/0267307) of prior record, hereinafter Lin.
Regarding claim 5, Viswanathan teaches the substrate of claim 1, but does not teach wherein a coefficient of thermal expansion (CTE) of the engineered filler material “is between” the CTE of the heat slug and the CTE of the substrate.
Lin (US 2019/0267307) also teaches a similar substrate (20, described as "core substrate 20" in para 43, see Figures 6-7), comprising a heat slug (30, (described as "heat dissipation slug 30" in para 43; see figures 6-7) disposed in a cavity (201, described as "aperture 201" in para 43 – see Figure 6) in the substrate (20), and
an engineered filler (40, described as "modified binding matrix 40” that includes “a resin adhesive 41 and a plurality of modulators 43 dispensed in the resin adhesive 41"). Lin further discloses wherein the CTE of the engineered filler material is adjustable (para 43, by varying modulators) and that induced stress due to thermal cycling depends not only on differences in CTE of different materials but also on width of the engineered filler material (40) - see para 43.
Given that induced stress due to thermal cycling is a known results effective variable and its dependence on difference in CTE of different interfacing materials is also known (as explained above), varying the relative CTE of the interfacing materials (i.e. CTEs of engineered filler material, heat slug and substrate, respectively) to specific value ranges to minimize induced stress at expected thermal cycling loads would not be cause for undue experimentation. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) see MPEP 2144.05. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the claimed invention to modify Viswanathan to adjust the CTEs of the materials interfacing with each to specific values to reduce stresses, such as wherein a coefficient of thermal expansion (CTE) of the engineered filler material “is between” the CTE of the heat slug and the CTE of the substrate. The ordinary artisan would have been motivated to modify Viswanathan at least for the purpose of minimizing induced stress due to thermal cycling (para 43 of Lin).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan and Molla, as applied to claim 9 above, further in view Joo (US 20200373270) of prior record, hereinafter Joo.
Regarding claims 10 and 11, Viswanathan teaches the IC package of claim 9, including that the engineered filler material (530) may be nano-silver (para 36), but does not teach wherein the engineered filler material is “a nano-copper” particle material (as recited in claim 10); OR (as recited in claim 11) that “the die attach material is the engineered filler material”. Joo (US 20200373270) teaches that die attach material may include any attaching material and/or adhesive material, and may include nano sinter materials, such as nanosilver and/or nanocopper (para 69). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan to so that nano-silver material is replaced with a known alternative such a nano-copper particle material, and be used for a known function; i.e. as a die attach material. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of using a known alternative material that is also known to serve as a die attach material, to adjust the thermal conductivity, electrical conductivity and/or the coefficient of thermal expansion of the engineered filler material, as per design requirements.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan and Molla, as applied to claim 9 above, further in view Dai (US 20120273939) of prior record, hereinafter Dai.
Regarding claim 12, Viswanathan teaches the IC package of claim 9, but does not teach “further comprising a via structure formed in the substrate, the via structure comprising: a via formed in the substrate; a conductive material disposed over a first side and a second side of the via; and the engineered filler material disposed in the via between the first and the second sides of the via”.
However, the claimed additional via is similar in concept to via 515 of Figure 5 of Viswanathan as it can also similarly contribute to heat transfer and reduction of stresses due to mismatch of coefficient of thermal expansion. Further, Dai (US 20120273939) (refer to Figure 1) teaches a via structure (comprising at least 102, 108 – see para 23; best seen in Figures 1A-1B) formed in a substrate (100, described as "substrate 100" in para 31 - see FIgure 1G), the via structure comprising: a via (102) formed (best seen in Figure 1A) in the substrate; a conductive material (108, described as disposed over a first side (i.e. upper side of 100 in orientation of figure 1G. such as conductive material of 122, para 29 – see Figure 1G) and a second side (i.e. bottom side 100 in orientation of figure 1G, such as such as conductive material of 132, para 32 – see Figure 1G) of the via; and an engineered filler material (108, such as "a copper-based composite" which has been engineered to have "coefficient of thermal expansion" to mitigate "thermal mechanical stress" - see para 23) is disposed in the via between the first and the second sides of the via (best seen in Figure 1G).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Viswanathan so that it further comprises “a via structure formed in the substrate, the via structure comprising: a via formed in the substrate; a conductive material disposed over a first side and a second side of the via; and the engineered filler material disposed in the via between the first and the second sides of the via”. The ordinary artisan would have been motivated to modify Viswanathan for at least the purpose of creating additional thermal paths for heat transfer while advantageously using an engineered filler material that not only has high thermal conductivity but also has CTE engineered to have "coefficient of thermal expansion" to mitigate "thermal mechanical stress" (see para 23 of Dai).
Response to Arguments
Applicant's arguments filed 10/10/2025 have been fully considered but they are not persuasive. Applicant refers to rejection of claim 2 (now cancelled but incorporated in claim 1) agreeing that Molla teaches “that wiring layer 48 is used for grounding” but argues that such grounding does not equate to “propagate a radio frequency (RF) signal” (especially see page 8, 1st three paragraph of applicant’s response. This argument is not persuasive. Refer to the revised rejection of claim 1 and similar claim 9, which explains that the grounding is part of the RF circuit and as such, involved in propagation of RF signal, noting that para 31 specifically talks about such grounding for “RF applications”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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