DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on11/3/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Detzel et al. US 2021/0234028 and Terano et al. US 2013/0134443.
Re claim 1, Detzel teaches a high-electron mobility transistor (100, fig4A, [55]), comprising:
a semiconductor body (101, fig4A, [56]) comprising a plurality of type III-nitride semiconductor layers (138, fig4A, [56]) stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels (106, fig4A, [55]) that are vertically spaced apart from one another;
source (112, fig4B, [43]) and drain (114, fig4B, [43]) electrodes that are laterally spaced apart from one another and in ohmic contact with each of the two-dimensional first charge type gas channels (112/114 in ohmic contact with 106, fig4, [43]);
a gate structure (118, fig4A, [60]) comprising a plurality of gate columns (122 in 104, fig4, [56, 60]) that extend into the semiconductor body (101, fig4A, [56]) and define gate fin portions (102, fig4, [56]) of the semiconductor body in between two of the gate columns,
wherein the gate structure (118, fig4A, [60]) is configured to control a conductive connection (116, fig4B, [43]) between the source and drain electrodes (112/114, fig4B, [43]) by controlling a conductive state of each of the two-dimensional first charge type gas channels within the gate fin portions.
Detzel teaches the gate fin portions are doped (136, fig4A, [53]), thereby locally reducing a concentration of free first charge type carriers within the gate fin portions ([53]).
Detzel also teaches diode 128 formed with the doped region 136 to provide an additional current blocking device to reduce both forward and reverse leakage current ([53]).
Detzel does not explicitly show wherein the gate fin portions are doped with second conductivity type dopant atoms.
Terano teaches forming p-type impurity diffusion region (13, fig8, [116]) adjacent to 2DEG region (5, fig8, [39]) between electrode (7, fig8, [116]) and region with 2DEG (5, fig8, [39]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Detzel and Terano to form p-type 136 layer in Detzel fig4. The motivation to do so is to reduce reverse leak current (Terano, [131,133]; Detzel, [53, 61]).
Detzel in view of Terano teaches wherein the gate fin portions are doped with second conductivity type dopant atoms, thereby locally reducing a concentration of free first charge type carriers within the gate fin portions (p-type impurity diffusion region 136 formed in sidewall and bottom surface of trench 104 on each side of 2DEG 106, fig4A).
Re claim 2, Detzel modified above teaches the high-electron mobility transistor of claim 1, wherein the gate columns comprise second conductivity type semiconductor material (p-type 136, fig4A, [52]) that directly interfaces with the type III-nitride semiconductor layers (138, fig4A, [56]), and wherein the second conductivity type dopant atoms are diffused out from the second conductivity type semiconductor material of the gate columns (form p-type impurity diffusion region 136 with lower dopant concentration under 122 with higher dopant concentration, fig4A, [45, 52]).
Re claim 3, Detzel modified above teaches the high-electron mobility transistor of claim 2, wherein the second conductivity type dopant atoms are substantially laterally homogeneously distributed across a width of each of the gate fin portions (p-type impurity diffusion region 136 formed in sidewall and bottom surface of trench 104 on each side of 2DEG 106 are homogeneous along 116 direction, fig4A).
Re claim 4, Detzel modified above teaches the high-electron mobility transistor of claim 3, wherein an average concentration of second conductivity type dopant atoms within the gate fin portions is greater than 5x1017 dopant atoms/cm3 (Terano, [133]; Detzel, [52]).
Re claim 5, Detzel modified above teaches the high-electron mobility transistor of claim 2, wherein the second conductivity type dopant atoms are laterally non-homogeneously distributed across a width of the each of the gate fin portions (Terano, p-type impurity diffusion region formed in sidewall and bottom surface of trench, fig9).
Re claim 6, Detzel modified above teaches the high-electron mobility transistor of claim 5, wherein the gate fin portions comprise first and second high doped regions that directly adjoin sidewalls of two immediately adjacent ones of the gate columns and a low doped region in between the first and second high doped regions, and wherein the gate fin portions have a lower second conductivity type dopant concentration in the low doped region than in the first and second high doped regions (Terano, p-type impurity diffusion region formed in sidewall and bottom surface of trench, fig9).
Re claim 7, Detzel modified above teaches the high-electron mobility transistor of claim 6, wherein the second conductivity type dopant atoms are substantially laterally homogeneously distributed across a width of each of the first and second high doped regions (Detzel, p-type impurity diffusion region formed in sidewall and bottom surface of trench 104 homogenous along width along 116 direction, fig4B).
Re claim 8, Detzel modified above teaches the high-electron mobility transistor of claim 5, wherein a concentration of the second conductivity type dopant atoms decreases proportionally moving away from the gate columns and towards a center of the gate fin portions (Terano, p-type impurity diffusion region formed in sidewall and bottom surface of trench, fig9).
Re claim 9, Detzel modified above teaches the high-electron mobility transistor of claim 1, wherein an average concentration of free first charge type carriers within an access region of the high-electron mobility transistor is greater than 5e12/cm2 per 500 nm vertical thickness, the access region being between the gate structure and the drain electrode (Detzel 102 about 5-80 nm thick fig4A [57] and 2DEG electron concentration ~10 13 cm-2 Terano [6]).
Re claim 10, Detzel modified above teaches the high-electron mobility transistor of claim 1, wherein the plurality of type III-nitride semiconductor layers comprises a plurality of layer pairs (Detzel, 138, fig4A, [56]), wherein each layer pair comprises a barrier layer (Detzel, 110 as AlyGa1-yN with higher Al concentration, fig4A, [56]) and a channel layer (Detzel, 108 AlyGa1-yN with lower Al concentration , fig4A, [56]), wherein each barrier layer is a layer of AIxGa1-xN and each channel layer is a layer of AlyGa1-yN, wherein x>y (Detzel, barrier layer with higher Al content, [56]).
Re claim 11, Detzel modified above teaches the high-electron mobility transistor of claim 10, wherein the wherein the gate columns comprise p-type AIGaN (Detzel, 136, fig4A, [52]; Terano, p-type impurity diffusion region formed in sidewall and bottom surface of trench, fig9).
Re claim 15, Detzel does not explicitly show the high-electron mobility transistor of claim 12, wherein the gate columns comprise second conductivity type semiconductor material that directly interfaces with the type III- nitride semiconductor layers.
Detzel teaches the gate fin portions are doped (136, fig4A, [53]), thereby locally reducing a concentration of free first charge type carriers within the gate fin portions ([53]).
Detzel also teaches diode 128 formed with the doped region 136 to provide an additional current blocking device to reduce both forward and reverse leakage current ([53]).
Terano teaches forming p-type impurity diffusion region (13, fig8, [116]) adjacent to 2DEG region (5, fig8, [39]) between electrode (7, fig8, [116]) and region with 2DEG (5, fig8, [39]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Detzel and Terano to form p-type 136 layer in Detzel fig4. The motivation to do so is to reduce reverse leak current (Terano, [131,133]; Detzel, [53, 61]).
Detzel in view of Terano teaches wherein the gate fin portions are doped with second conductivity type dopant atoms, thereby locally reducing a concentration of free first charge type carriers within the gate fin portions (p-type impurity diffusion region 136 formed in sidewall and bottom surface of trench 104 on each side of 2DEG 106, fig4A).
Claim(s) 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Detzel et al. US 2021/0234028 and Pei et al. US 2021/0399145.
Re claim 12, Detzel teaches a high-electron mobility transistor (100, fig4A, 7A or 8C, [64]), comprising:
a semiconductor body (101, fig4A or 7A, [64]) comprising a plurality of type III-nitride semiconductor layers (110/108, fig4A or 7A, [64]) stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels (106, fig4A or 7A, [55]) that are vertically spaced apart from one another;
source (112, fig4B or 7B, [43]) and drain electrodes (114, fig4B or 7B, [43]) that are laterally spaced apart from one another and in ohmic contact with each of the two-dimensional first charge type gas channels (112/114 in ohmic contact with 106, fig4or 7, [43]);
a gate structure (118, fig4A or 7A, [60]) comprising a plurality of gate columns (122 in 104, fig4 or 7, [56, 60]) that extend into the semiconductor body (101, fig4A or 7A, [56]) and define gate fin portions (102, fig4 or 7, [56]) of the semiconductor body in between two of the gate columns,
wherein the gate structure (118, fig4A or 7A, [60]) is configured to control a conductive connection (116, fig4B or 7B, [43]) between the source and drain electrodes (112/114, fig4B or 7B, [43]) by controlling a conductive state of each of the two-dimensional first charge type gas channels within the gate fin portions, and
wherein the high-electron mobility transistor is a normally-off device ([45]), and
Detzel does not explicitly show wherein a width of the gate fin portions is greater than 100nm for embodiment in fig4A, 7A or 8C.
Detzel teaches gate fin width equal to 2x thickness of 136 plus width of 102 in fig4A with thickness of 136 about the same as 110 between 40-80nm and 102 of 100nm or less in fig2A ([57]); 102 with width in region along II’ greater than 135 between 100nm to 300nm as shown in fig7A and 7B and with of 102 between top part of 104 close to 114 in fig8C greater than the width of trench 104 with a width of 135 ([64]).
Pei teaches Wa ranges from 10-1000nm and Wb ranges from 10nm to over 1000nm with Wb/(Wa+Wb) ranges from 5 to 95% (fig1A and 3C, [56]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Detzel and Pei to tune the shape and width of the gate fin portion to tune the width and thickness of the channel and barrier layer. The motivation to do so is to achieve optimized device (Detzel, [64]; Pei, [103]).
Re claim 14, Detzel modified above teaches the high-electron mobility transistor of claim 12, wherein the width of the gate fin portions is between 110 nm and 300 nm (102 with width greater than 135 between 100nm to 300nm, fig7A, [64]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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