DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 2017/0179078) (“Jung”).
With regard to claim 1, fig. 6 of Jung discloses an integrated circuit component 20 comprising: a first substrate 1100 comprising a first surface 1101 and a second surface 1103 opposite the first surface 1101; a first die 1200 mounted on the first surface 1101 of the first substrate 1100; a second die (left 1400) mounted on the second surface 1103 of the first substrate 1100; and a second substrate 1500, wherein the first substrate 1100 is mounted on the second substrate 1500, wherein a cavity 1509 is defined in the second substrate 1500, wherein the cavity 1509 extends from a top surface 1503 of the second substrate 1500 to a bottom surface 1501 of the second substrate 1500, wherein the second die 1200 is positioned in the cavity 1509 of the second substrate 1500 such that the second substrate 1500 surrounds the second die (left 1400).
With regard to claim 2, fig. 6 of Jung discloses of the first die 1200 is a processor die (“microprocessor”, par [0032]).
With regard to claim 4, fig. 6 of Jung discloses that the second die (left 1400) is a memory die (“memory die”, par [0032]).
With regard to claim 7, fig. 6 of Jung discloses a third die (right 1400) mounted on the second surface 1103 of the first substrate 1100, wherein the third die (right 1400) is disposed in the cavity 1509 of the second substrate 1500.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wallace (US 2003/0183914).
With regard to claim 19, fig. 4 of Wallace discloses an integrated circuit component comprising: a first substrate 110 comprising a first surface (top of 110) and a second surface (bottom of 110) opposite the first surface (top of 110); a first die 144 mounted on the first surface (top of 110) of the first substrate 110; a second die 120 mounted on the second surface (bottom of 110) of the first substrate 110; and a second substrate 112, wherein the first substrate 110 is mounted on the second substrate 112, wherein the second surface (bottom of 110) of the first substrate 110 is opposite the second substrate 112, wherein the second substrate 112 comprises means for accommodating 132 (The limitation “means for accommodating the second die” does not have sufficient definite meaning as the name for a structure, thus is interpreted as a mean-plus-function limitation under 35 U.S.C. 112(f). The broadest reasonable interpretation of a claim limitation that invokes 35 U.S.C. 112(f) is the structure, material or act described in the specification as performing the entire claimed function and equivalents to the disclosed structure. See MPEP sec 2181. In this case the “means for accommodating” would be a cavity.) the second die 120.
With regard to claim 20, fig. 4 of Wallace discloses a stack comprising the first substrate 110, the first die 144, the second die 120, and the second substrate 112 has a thickness less than 1.3 millimeters (“thickness of the package is about 0.7 millimeters”, claim 5 of Wallace).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0179078) (“Jung”) in view of Myasishchev et al. (US 2021/0066273) (“Myasishchev”).
With regard to claim 3. Jung does not disclose that the first die comprises a multi-chip processor package.
However, fig. 4A of Myasishchev discloses that the first die 100 comprises a multi-chip processor package (“multi-chip processor package”, par [0047]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the first die of Jung with the multi-chip processor package as taught in Myasishchev in order to provide dies that include transistors that are fabricated at different process nodes. See par [0047] of Myasishchev.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0179078) (“Jung”) in view of Hong (US 2022/0173072).
With regard to claim 5, Jung does not disclose second die is a memory sub-package comprising a logic controller die and a stack of memory dies.
However, fig. 3 of Hong disclose second die 301 is a memory sub-package comprising a logic controller die 310 and a stack of memory dies 320.
Therefore, it would have been obvious to one of ordinary skill in the art to form the memory device of Hong with the base die including a logic device as taught in Hong in order to provide a shorted interconnect for controlling the memory devices. See par [0029] of Hong.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0179078) (“Jung”) in view of Wallace (US 2003/0183914).
With regard to claim 6, Jung does not disclose a stack comprising the first substrate, the first die, the second die, and the second substrate has a thickness less than 1.3 millimeters.
However, fig. 2c of Wallace discloses a stack comprising the first substrate 110, the first die 144, the second die 120, and the second substrate 112 has a thickness less than 1.3 millimeters (“thickness of the package is about 0.7 millimeters”, claim 5 of Wallace).
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor package of Jung with the .7 millimeters thickness as taught in Wallace in order to provide a thin package. See par [0024] of Wallace.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0179078) (“Jung”) in view of Zhong et al. (US 2020/0176431) (“Zhong”).
With regard to claim 8, fig. 6 of Jung discloses that the first substrate 1100 has four edges in a rectangular shape.
Jung does not disclose further comprising a stiffener, wherein, for each of the four edges, at least part of the stiffener is disposed within 10% of an edge-to-edge width along the corresponding edge.
However, fig. 1 of Zhong discloses further comprising a stiffener 160, wherein, for each of the four edges, at least part of the stiffener 160 is disposed within 10% of an edge-to-edge width along the corresponding edge 101.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interconnection structure layer of Jung with the stiffener ring as taught in Zhong in order provide mechanical balancing of the substrate. See par [0024] of Zhong.
With regard to claim 9, Jung does not disclose a stiffener disposed near all edges of the first surface of the first substrate.
However, fig. 1 of Zhong discloses a stiffener 160 disposed near all edges of the first surface 103 of the first substrate 102.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interconnection structure layer of Jung with the stiffener ring as taught in Zhong in order provide mechanical balancing of the substrate. See par [0024] of Zhong.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0179078) (“Jung”) in view of Patil et al. (US 2022/0278016) (“Patil”).
With regard to claim 10, Jung does not disclose a heat spreader is adjacent the second die.
However, fig. 2 of Patil discloses a heat spreader 232 is adjacent the second die 218.
Therefore, it would have been obvious to one of ordinary skill in the art to form the second die of Jung with the seat sink as taught in Patil in order to conduct heat away from the IC package. See par [0044] of Patil.
With regard to claim 11, fig. 6 of Jung disclose a device (“laptop computer”, par [0104]) comprising the integrated circuit component (“semiconductor package”, par [0101]).
Jung does not disclose a display, wherein the display is adjacent the heat spreader.
However, fig. 10 of Patil discloses a display 606, wherein the display 606 is adjacent the heat spreader 604.
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor package of Jung with the major cooling solution and display as taught in Patil in order to remove excess heat generated in the integrated circuit package. See par [0001] of Patil.
With regard to claim 12, Jung does not disclose the device further comprising a cover, wherein the cover is adjacent the heat spreader.
However, fig. 10 of Patil discloses that the device further comprising a cover 606, wherein the cover 606 is adjacent the heat spreader 604.
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor package of Jung with the major cooling solution and display as taught in Patil in order to remove excess heat generated in the integrated circuit package. See par [0001] of Patil.
With regard to claim 13, fig. 6 of Jung discloses that the device is a laptop (“laptop computer”, par [0104]) with a display portion and detachable keyboard portion, wherein the integrated circuit component 20 is disposed on the display portion (“display”, par [0101]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mokler et al. (US 2019/0098802) (“Mokler”) in view of Wallace (US 2003/0183914).
With regard to claim 14, fig. 2 of Mokler discloses an integrated circuit component comprising: a first substrate 106 comprising a first surface (top of 106) and a second surface (bottom of 106) opposite the first surface (top of 106), wherein the first substrate 106 has a length between 5 and 50 millimeters (“15 millimeters by 15 millimeters”, par [0029]), a width between 5 and 50 millimeters (“15 millimeters by 15 millimeters”, par [0029]), a die mounted 108 on the second surface (bottom of 106) of the first substrate 106; and a second substrate 102, wherein the first substrate 106 is mounted on the second substrate 102, wherein a cavity 112 is defined in the second substrate 102, wherein the die 108 is positioned in the cavity 112 of the second substrate 102,
Mokler does not disclose that the first substrate has a thickness between 0.1 and 2 millimeters, wherein a stack comprising the first substrate, the die, and the second substrate has a thickness less than 1 millimeter.
However, fig. 4 of Wallace discloses that the first substrate 110 has a thickness between 0.1 and 2 millimeters (“thickness of the package is about 0.7 millimeters”, claim 5 of Wallace), wherein a stack comprising the first substrate 110, the die 120, and the second substrate 112 has a thickness less than 1 millimeter (“thickness of the package is about 0.7 millimeters”, claim 5 of Wallace).
Therefore, it would have been obvious to one of ordinary skill in the art to form the package substrate and circuit board of Mokler with the thickness of Wallace in order to provide a thin package. See par [0031] of Wallace.
With regard to claim 15, fig. 2 of Mokler discloses comprising a second die 108 mounted on the first surface (bottom of 106) of the first substrate 106.
With regard to claim 16, Mokler disclose a stack comprising the first substrate 106, the die 108, the second die 110, and the second substrate 102
Mokler does not disclose the stack has a thickness less than 1.3 millimeters.
However, fig. 4 of Wallace discloses that the stack 400 has a thickness less than 1.3 millimeters (“thickness of the package is about 0.7 millimeters”, claim 5 of Wallace).
Therefore, it would have been obvious to one of ordinary skill in the art to form the package substrate and circuit board of Mokler with the thickness of Wallace in order to provide a thin package. See par [0031] of Wallace.
Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mokler et al. (US 2019/0098802) (“Mokler”), Wallace (US 2003/0183914), and Myasishchev et al. (US 2021/0066273) (“Myasishchev”).
With regard to claim 17, Mokler does not disclose that the second die comprises a multi-chip processor package.
However, fig. 4A of Myasishchev discloses that the first die 100 comprises a multi-chip processor package (“multi-chip package”, par [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the first die of Jung with the multi-chip processor package as taught in Myasishchev in order to provide dies that include transistors that are fabricated at different process nodes. See par [0047] of Myasishchev.
Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mokler et al. (US 2019/0098802) (“Mokler”), Wallace (US 2003/0183914), and Jung et al. (US 2017/0179078) (“Jung”).
With regard to claim 18, Mokler does not disclose that the die is a memory die.
However, fig. 6 of Jung discloses that the die 1400 is a memory die (“memory device”, par [0047]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the electronic components of Mokler with the memory device as taught in Jung in order to provide a high-performance memory device such as a HBM chip. See par [0047] of Jung.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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