DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The Response to Election/Restriction filed 07/27/2026 has been received and considered. Claims 10-20 are withdrawn from further consideration. Claims 1-9 are elected with traverse and presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Examiner would like to point out that any reference to specific figures, pages, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Paul R. Schumacher, (Schumacher hereinafter), U.S. Patent 9529946, taken in view of Chi Bun Chan, (Chan hereinafter), U.S. Patent 7673201.
As to claim 1, Schumacher discloses a method comprising… a circuit design, wherein the circuit design is mapped onto integrated circuit (IC) devices (see ‘A set of configuration bits can be used to program programmable circuitry of an IC such as an FPGA. The configuration bit(s) typically are referred to as a “configuration bitstream.” In general, programmable circuitry is not operational or functional without first loading a configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuitry’ in col. 4, line 66 to col. 5, line 6); instrumenting the circuit design mapped onto the IC devices (see “the particular number of IP modeling blocks and corresponding monitors can vary according to need. The particular configuration bitstream that is loaded into the IC to implement configurable hardware platform 400 will define the particular number of IP modeling blocks implemented“ in col. 13, line 62 to col. 14, line 5) by inserting a first change detection circuit and a first synchronization circuit, the first synchronization circuit connected to the first change detection circuit and configured to (see “system can program the IP modeling blocks of the configurable hardware platform within the IC. Each IP modeling block involved in the emulation can be programmed with the appropriate performance profile specifying the modeling data needed for that IP modeling block to emulate the segment associated with the IP modeling block. Each IP modeling block can be programmed with a performance profile specific to that IP modeling block, thereby allowing each IP modeling block to be programmed independently of the others“ in col. 25, lines 51-60) stop emulation on one of the IC devices based on an output of the first change detection circuit and completion of a first one or more emulation cycles (see “The ability to dynamically enable IP modeling blocks or portions thereof is further enhanced in that modeling data can be provided to any one or more or all of the IP modeling blocks during emulation to change behaviors such as traffic generation or the particular power profile that is being implemented. For example, traffic generation can be increased or decreased (e.g., stopped) dynamically responsive to providing the IP modeling block with new or different modeling data during the emulation. Similarly, the power profile can be changed to increase or decrease (e.g., stop operation of the power emulation circuit) the toggle rate of the power emulation circuitry within an IP modeling block dynamically during emulation by providing new or updated modeling data to the IP modeling block” in col. 29, lines 33-46); and providing the IC devices for emulation (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20).
While Schumacher discloses a circuit design, Schumacher fails to disclose receiving
Chan discloses receiving (See “Circuit design 120 can be a circuit, or portion of a circuit, that is implemented within the programmable IC. For example, circuit design 120 can be implemented within programmable IC by loading configuration data, e.g., a bitstream, into configuration memory cells of the programmable IC” in col. 6, lines 15-21).
Schumacher and Chan are analogous art because they are related to emulation.
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Chan with Schumacher, because Chan points out that "the clock control module can include a snapshot module that stores the operational state of the circuit design at various times during operation of the circuit design. Some time after acquisition and storage of an operational state of the circuit design, a state restoration signal can be received. Responsive to the state restoration signal, another module of the clock control circuit, referred to as the correction module, can recall the most recent operational state stored for the circuit design and load that operational state into the relevant portions of configuration memory of the programmable IC” (see col. 5, lines 20-30), and as a result, Chan reports that "[t]his process effectively implements the most recent operational state of the circuit design in existence some number of clock cycles prior to the receipt of the state restoration signal. The clock of the circuit design then can be advanced in stepwise fashion a number of clock cycles until the circuit design is in the exact operational state that existed at the time the state restoration signal was received, thereby restoring the desired operational state in the circuit design for analysis" (see col. 5, lines 30-38).
As to claim 2, Schumacher discloses wherein the first change detection circuit and the first synchronization circuit are inserted in a first IC device of the IC devices (see “system can program the IP modeling blocks of the configurable hardware platform within the IC. Each IP modeling block involved in the emulation can be programmed with the appropriate performance profile specifying the modeling data needed for that IP modeling block to emulate the segment associated with the IP modeling block. Each IP modeling block can be programmed with a performance profile specific to that IP modeling block, thereby allowing each IP modeling block to be programmed independently of the others“ in col. 25, lines 51-60).
As to claim 3, Schumacher discloses wherein an input of the first change detection circuit is connected to a first circuit element configured to output a first signal (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20) based on a first clock signal having a frequency that is less than the frequency of an emulation clock signal (see “specify a clock rate and/or a toggle rate to be implemented within the IP modeling block during emulation“ in col. 12, lines 43-47).
As to claim 4, Schumacher discloses wherein the first change detection circuit is configured to detect a change in the first signal (see “Monitors 425-435 can be coupled to communication link 470, 475, and 480, respectively, to measure various parameters during emulation. Monitors 425-435 can be configured to detect or identify information on communication links 470-480 such as, for example, timestamps of start and end times of address information, data, and IP modeling block execution (e.g., execution of a sequence or particular number of commands)” in col. 13, lines 21-28), and output a change detection signal based on detecting the change in the first signal (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20).
As to claim 5, Schumacher discloses wherein the first one or more emulation cycles corresponds to a propagation time of the first signal from the first IC device of the IC devices to a second IC device of the IC devices (see “host can determine a data flow in part by calculating an amount of time for the circuit module implementation of the first segment to generate an output responsive to receiving an input. The host calculates a parameter of the performance profile representing that amount of time. The parameter is used during emulation, for example, to control the amount of time required for the IP modeling block to generate a result and, thus, specifies the amount of time that the IP modeling block waits responsive to receiving an input before sending an output“ in col. 23, lines 23-32).
As to claim 6, Schumacher discloses wherein instrumenting the circuit design further comprises inserting a second change detection circuit and a second synchronization circuit in a second IC device of the IC devices, wherein the second synchronization circuit is connected to the first synchronization circuit (see “system can program the IP modeling blocks of the configurable hardware platform within the IC. Each IP modeling block involved in the emulation can be programmed with the appropriate performance profile specifying the modeling data needed for that IP modeling block to emulate the segment associated with the IP modeling block. Each IP modeling block can be programmed with a performance profile specific to that IP modeling block, thereby allowing each IP modeling block to be programmed independently of the others“ in col. 25, lines 51-60).
As to claim 7, Schumacher discloses wherein the second synchronization circuit is configured to stop emulation on the IC devices (see “The ability to dynamically enable IP modeling blocks or portions thereof is further enhanced in that modeling data can be provided to any one or more or all of the IP modeling blocks during emulation to change behaviors such as traffic generation or the particular power profile that is being implemented. For example, traffic generation can be increased or decreased (e.g., stopped) dynamically responsive to providing the IP modeling block with new or different modeling data during the emulation. Similarly, the power profile can be changed to increase or decrease (e.g., stop operation of the power emulation circuit) the toggle rate of the power emulation circuitry within an IP modeling block dynamically during emulation by providing new or updated modeling data to the IP modeling block” in col. 29, lines 33-46) based on an output of the second change detection circuit (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20) and completion of a second one or more emulation cycles, the second one or more emulation cycles are subsequent to the first one or more emulation cycles (see “the traffic pattern that is developed for an IP modeling block is determined or derived from an analysis of the data flow for the segment the IP modeling block is to implement through emulation. The host can profile each segment of the design selected for implementation in hardware. In profiling the various segments of the design, the host determines one or more parameters of the data flow, also referred to as execution attributes of the segment, which include, but are not limited to, the number of processing cycles needed for the segment to execute” in col. 22, lines 43-52).
As to claim 8, Schumacher discloses wherein instrumenting the circuit design further comprises inserting a second change detection circuit in the first IC device, wherein the first synchronization circuit is connected to the second change detection circuit (see “system can program the IP modeling blocks of the configurable hardware platform within the IC. Each IP modeling block involved in the emulation can be programmed with the appropriate performance profile specifying the modeling data needed for that IP modeling block to emulate the segment associated with the IP modeling block. Each IP modeling block can be programmed with a performance profile specific to that IP modeling block, thereby allowing each IP modeling block to be programmed independently of the others“ in col. 25, lines 51-60), and configured to stop emulation in the IC devices (see “The ability to dynamically enable IP modeling blocks or portions thereof is further enhanced in that modeling data can be provided to any one or more or all of the IP modeling blocks during emulation to change behaviors such as traffic generation or the particular power profile that is being implemented. For example, traffic generation can be increased or decreased (e.g., stopped) dynamically responsive to providing the IP modeling block with new or different modeling data during the emulation. Similarly, the power profile can be changed to increase or decrease (e.g., stop operation of the power emulation circuit) the toggle rate of the power emulation circuitry within an IP modeling block dynamically during emulation by providing new or updated modeling data to the IP modeling block” in col. 29, lines 33-46) based on an output of the second change detection circuit (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20).
As to claim 9, Schumacher discloses wherein an input of the second change detection circuit is connected to a second circuit element configured to output a second signal (see “system can program the IP modeling blocks of the configurable hardware platform within the IC. Each IP modeling block involved in the emulation can be programmed with the appropriate performance profile specifying the modeling data needed for that IP modeling block to emulate the segment associated with the IP modeling block. Each IP modeling block can be programmed with a performance profile specific to that IP modeling block, thereby allowing each IP modeling block to be programmed independently of the others“ in col. 25, lines 51-60) based on a second clock signal having a frequency that is less than the frequency of an emulation clock signal (see “specify a clock rate and/or a toggle rate to be implemented within the IP modeling block during emulation“ in col. 12, lines 43-47), and wherein the second change detection circuit is configured to output a second change detection signal (see “Instrumenting the design refers to inserting program code, e.g., a driver, that allows the processor of the design to communicate and interact with an IP modeling block emulating a circuit module implementation of a segment selected for hardware implementation. The program code inserted into the design, e.g., the driver, when executed, causes the processor to provide data as input to the IP modeling block, receive data output from the IP modeling block” in col. 25, lines 13-20) based on detecting a change in the second signal (see “Monitors 425-435 can be coupled to communication link 470, 475, and 480, respectively, to measure various parameters during emulation. Monitors 425-435 can be configured to detect or identify information on communication links 470-480 such as, for example, timestamps of start and end times of address information, data, and IP modeling block execution (e.g., execution of a sequence or particular number of commands)” in col. 13, lines 21-28).
Response to Arguments
Applicant's election with traverse of Species I (claims 1-9) in the reply is acknowledged. Applicant argues, (see page 6, next to last paragraph to page 7, 2nd paragraph):
‘… The Office states that the identified species are mutually exclusive because Example 1 purportedly uses no concentrator circuitry or signal voltage change, Example 2 purportedly uses no synchronization or signal voltage change, and Example 3 purportedly uses no synchronization or concentrator circuitry. Applicant respectfully submits that the record does not support treating the identified examples as patentably distinct species requiring separate searches and examination. Rather, the specification describes a common dynamic emulation-control architecture in which detector/change-detection circuitry detects a signal change within IC devices and corresponding ready-network, synchronization, or concentrator circuitry controls stopping of emulation based on that detection.
For example, the specification explains that the emulation system includes detector circuitry within the IC devices to detect when a change to a signal occurred, that the detector circuitry is connected to ready-network circuitry, and that the emulation process is stopped based on detecting the change to the signal. The specification further explains that the host system and/or compiler inserts a change detection circuit and a synchronization circuit in an IC device, with the synchronization circuit connected to the change detection circuit and stopping emulation based on the output signal of the change detection circuit. Thus, the different claim groupings are directed to related aspects of the same disclosed emulation-control mechanism, not unrelated inventions requiring restriction…’
Examiner's response: Applicant's argument is not persuasive. As pointed out in the previous Office Action, the claimed “species are independent or distinct because the claims to the different species recite… mutually exclusive characteristics”. The traversal is on the ground(s) that “the specification describes a common dynamic emulation-control architecture… the different claim groupings are directed to related aspects of the same disclosed emulation-control mechanism, not unrelated inventions requiring restriction”; however, the claimed species are distinct. As pointed out in the previous Office Action, ‘[t]his application contains claims directed to the following patentably distinct species of first, second, and third examples…’. The requirement is still deemed proper and is therefore made FINAL.
Conclusion
Examiner would like to point out that any reference to specific figures, pages, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN CARLOS OCHOA whose telephone number is (571)272-2625. The examiner can normally be reached Mondays, Tuesdays, Thursdays, and Fridays 9:30AM - 8:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Chavez can be reached at 571-270-1104. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUAN C OCHOA/Primary Examiner, Art Unit 2186
Prosecution Insights