DETAILED ACTION
This office action is in response to applicant’s amendment filed on September 12, 2025. Claims 1-20 are under consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-11, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pratap et al. (US 2022/0196942 A1, herein “Pratap”).
Regarding Claims 8 and 15-16, Pratap discloses a package device, comprising:
a carrier (1220 in Fig. 12);
a die (substrate and component SOC thereon) disposed over the carrier (1220) ; and
a photonic interposer (optical coupler 1212) disposed over and optically coupled to the die (substrate and component SOC thereon), wherein the photonic interposer has an exterior lateral surface,
wherein the die has a first surface facing away (top surface of the substrate) from the carrier, and a first portion of the first surface is exposed from the photonic interposer (optical coupler 1212),
wherein, in a cross-section, a distance between the first side and a second side of the exterior lateral surface of the photonic interposer is greater than a width of the die (SOC). See Fig. 12.
Claim 9. Pratap discloses the first portion of the first surface of the die is exposed from an opening defined by four sides of an interior lateral surface of the photonic interposer, and wherein the opening is in the middle of the photonic interposer (optical coupler 1212 in Fig. 12).
Claim 10. In the top view, a first area of the photonic interposer (1212) is greater than a second area of the die (SOC). See Fig. 12.
Claim 11. In the top view, four sides of the second area of the die are covered by the first area of the photonic interposer (See Fig. 1, bottom surface of “substrate” is electrically coupled to the “motherboard” via BGA 122).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Pratap in view of Lee et al. (US 2006/0208165 A1, herein “Lee”).
Regarding claim 1 and 4, Pratap discloses a package device comprising:
a carrier (1220 in Fig. 12); and
a die (photonics package 1202) disposed over the carrier (1220) and having a first surface (bottom surface of 1202) facing the carrier and a second surface (top surface of 1202) opposite to the first surface,
wherein the first surface of the die is configured to electrically connect (ball grid array [BGA] 122, Para [0032]) to the carrier and the second surface of the die is configured to optically connect (optical paths 1282, 1283) to the carrier.
However, Pratap does not teach a plurality of photonic bumps disposed on and optically connected to the second surface of the die.
Lee teaches a plurality of photonic bumps (20, 54, 68 as exemplifies in Fig. 6) disposed on an electro-optical chip (12) and optically connected to the second surface of the die in the case of two optoelectronic integrated circuits (“OEICs”) that are connected together (Para [0007]). Since the photonic bumps connect the two chip (12), they would function to guide light from one chip to the other regardless of whether they protrude from the first chip (12) or the second chip (12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the plurality of photonic bumps disclosed by Lee can be modified to the die substrate of Pratap as they are from the same field of endeavor. One motivation for implementing photonic bumps for the purpose of interconnecting multiple photonic dies without the need of optical to electrical conversion, and vice versa, which would require additional components such as VCSEL chip and/or a photodiode (Para [0007]).
Claims 2-3. Pratap in view of Lee (herein “Pratap / Lee”) teach the package device of claim 1, and Pratap / Lee teach the plurality of photonic bumps are arranged along a direction perpendicular to the second surface and they are non-overlapping (Lee: Fig. 6).
Pratap / Lee do not teach the photonic bumps are disposed on a peripheral region of the second surface with a central region is surrounded by the peripheral region.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the photonic bumps would function to couple light from one die to another on the periphery of the two dies, and in the instant case, the modification of would have the photonic bumps coupled between the carrier (Pratap) to a photonic die (Lee: die 12) on the periphery. The benefits of this modification would allow of external components such as optical connectors to connect to the package device from the edge.
Claim 5. Pratap / Lee teach further comprising a plurality of conductive pillars disposed over the carrier and configured to transmit an electrical signal, wherein the conductive pillars have an upper surface at substantially the same elevation with a lower surface of the photonic bumps which contacts the second surface of the die. Fig. 6 in Lee’s disclosure shows the photonic bumps are at the same elevation as the BGA (16). Lee further teaches the BGA 16 or “electrical joints 16” can be pull-up solder pillars (Para [0009]).
Claim 6. Pratap / Lee teach the package device of claim 5, but Pratap / Lee do not explicitly teach the conductive pillars surrounds the die and are covered by a molding compound. However, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize molding compound is well known in the manufacturing of semiconductor chip as a protective material that encapsulates the components from environmental damage and thermal expansion differences. Therefore, it would have been obvious for a practitioner to employ the molding compound to cover the conductive pillars in Pratap / Lee package device for the same purpose that is well-known to practitioners in the art of semiconductor manufacturing.
Claim 7. Pratap / Lee teach the package device of claim 1 and Pratap / Lee further teach optical pillars as alternative to photonic bumps (Lee: Figs. 7-8). The pillar in Lee comprises of a core (photonic bump) formed of material such as PMMA (Para [0060]) and a cladding material can be an optical grade polymer (Para [0021]). Lee further teaches the cladding layer prevents the underfill from contacting the optical bump and interfere with the transmission of light through the optical bump (Para [0046]). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include optical pillars (photonic bumps with external cladding layer) in regions where underfills or flux residues can contaminate the photonic bumps and interfere with light transmission (Para [0046], [0078]).
Regarding claim 12. Pratap discloses the package device of claim 8, but Pratap does not disclose a plurality of optical pillars disposed outside the photonic interposer, wherein an upper surface of the optical pillars are at substantially the same elevation with a lower surface of the photonic interposer.
Lee teaches optical pillars for providing optical connections between two chips (12). The pillar in Lee comprises of a core (photonic bump) formed of material such as PMMA (Para [0060]) and a cladding material can be an optical grade polymer (Para [0021]). Lee further teaches the cladding layer prevents the underfill from contacting the optical bump and interfere with the transmission of light through the optical bump (Para [0046]). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include optical pillars (photonic bumps with external cladding layer) in regions where underfills or flux residues can contaminate the photonic bumps and interfere with light transmission (Para [0046], [0078]). Furthermore, the placement of the optical pillars is design specific to the architecture of the interposer with respect to the photonic chip or plurality of photonic chip as required by the package.
Claims 13-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pratap in view of Mazed (US 11,320,588 B1, herein “Mazed”).
Regarding claim 13, Pratap discloses the invention of claim 8, but does not disclose plurality of bonding wires connected to a plurality of optical I/O units at the first surface of the die. Pratap discloses the photonic bonding wires are optically coupled to an upper surface or an interior lateral surface of the photonic interposer.
Mazed teaches the optical components (LiDAR components) can be optically coupled by photonic wire bond (PWB) waveguides on the common master platform substrate. Mazed further teaches adiabatic taper waveguides were optical interconnection to avoid on board optical coupling loss. Alternatively, adiabatic taper can be replaced by a photonic wire bond waveguide, enabled by direct-write three-dimensional laser lithography based on two-photon polymerization (Col. 35, lines 34-63 and Col. 36, lines 27-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the photonic wire bond as taught in Mazed would be adaptable to be written in-situ on the die substrate and the interior lateral surface of the photonic interposer to provide efficient optical signal interconnection (e.g., chip-to-chip and chip-to-fiber). Furthermore, it would have been obvious to provide a plurality of second photonic bonding wires connected to a plurality of second optical I/O units at the first surface of the die, wherein the first photonic bonding wires are higher than the second photonic bonding wires with respect to the first surface (offset). Providing additional I/O ports would have been obvious to scale up the package device wherein the offsetting the bonding wires for the respective I/O ports would be necessary to prevent crosswire.
Regarding claims 14 and 18, Pratap in view of Mazed teach the package device of claim 13, but Pratap in view of Mazed do not explicitly teach the photonic bonding wires comprise a curve shape having a highest point higher than the upper surface of the photonic interposer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide curve shape having a highest point higher than the upper surface of the photonic interposer for easy access to connect or disconnect the bonding wires.
Regarding claims 19-20. Pratap in view of Mazed teach the package device of claim 18, but Pratap in view of Mazed are silent to the bonding wires overlap or non-overlapping. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the bonding wires overlap or non-overlapping is a design choice with respect the parameters given the complexity and density of the package device. Therefore, it would have been obvious for a practitioner to provide bonding non-overlapping wires in designs that do not require dense numbers of components versus overlapping wires would be unavoidable in densely packed architecture.
Regarding claim 17, Pratap teaches optical fibers can connect to the package device exterior lateral surface by an adhesive material (Para [0038]) and further suggests plurality of optical couplers may be attached to the photonic packages (Para [0017]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to scale the number of optical fiber I/O necessary per design specific parameters. One would be motivated to provide four optical fiber I/O ports to maximize the geometry of the package device.
Response to Arguments
Applicant’s arguments with respect to claims 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Arguments pertaining to claims 8-20 have been addressed and clarified with respect the amended limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874