Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
(Text within parentheses is either a missing or a corrected information to character(s) in bold.)
[0019] Figure 7 illustrates another(an) OR gate timing models () with node transitions according to one or more embodiments of the present disclosure.
[There are no other OR gate timing model mentioned]
[0037] To obtain TCPs of a NOR gate in standard ECSM syntax, the voltage transition of the intermediate node X 206 in different regions is first modeled as indicated with the R prefix in Figures 3A and 3B. In R - 1, M3 is in an off state
[There is no R in Figures 3A and 3B. But there are “Region.”]
[There are no R – 1 in Figures 3A and 3B, but there is Region – I]
[0038]
t
0
=
(
V
t
h
4
+
V
t
s
a
t
)
V
d
d
T
R
+
C
M
β
S
M
4
[There is no real explanation of what are
V
t
s
a
t
and
β
S
M
4
]
[0039] In region R - 2 302 in Figure 3A, …
[There is no R – 2 in Figure 3A, but there is Region-II]
[0045] Again, in R - 3, the change in VX is equal and opposite to Vin_b, hence by solving KCL at node X, one gets:
[There is no R – 3 in any figure, but there are Region-III in Fig. 3B, Fig. 4B, and R-III in Fig. 5A]
[0047] Finally, in R - 4, VX reaches a high constant value, as shown below:
[There is no R – 4 in any figure]
Appropriate correction is required.
Claim Objections
Claim 4 and 9-11 objected to because of the following informalities: “the updated timing model” mentioned in claim 4 and 9-11 is inconsistent with the previously defined terminology “updated aging aware timing model” in claim 1.
Claim 5 and 16 objected to because of the following informalities: “the updated timing model” mentioned in claim 5 and 16 is inconsistent with the previously defined terminology “updated aging aware timing model” in claim 1.
Further, the “the multi- stage logic cell” mentioned in the last line of claim 5 is also inconsistent with the previously defined terminology “the multi- stage digital cell.”
Claim 15 objected to because of the following informalities: “the updated timing model” mentioned in claim 15 on line 1 is inconsistent with the previously defined terminology “updated aging aware timing model” in claim 12.
Appropriate correction is required.
Allowable Subject Matter
Claims 1-3, 6-7, 12-14, 17-18, and 20 allowed.
The following is the examiner’s statement of reasons for allowance:
Regarding claim 1
Aditya Bansal et. al. (US 20130254731 A1) hereinafter Bansal discloses
A method for estimating a timing performance of a circuit block, comprising:
(Bansal, Abstract: “Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. “)
(Bansal, p. 1, “[0003] The present invention relates to the reliability of integrated circuits, and more particularly to a method for estimating delay deterioration in integrated circuits due to device degradation.”)
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
(Bansal, p. 3 [0028] “Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram is illustrated of a diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles.”)
Bansal does not teach
determining a timing model for one or more circuit components based on threshold crossing points for each circuit component in a circuit block
But Bansal discloses an inverse of it
(Bansal, p. 3, “A functional expression for a change in threshold-voltage can be expressed as
∆
V
T
=
f
(
V
d
d
,
T
,
t
o
n
,
t
o
f
f
,
S
)
where
V
d
d
is the operating voltage, T is the operating temperature,
t
o
n
and
t
o
f
f
are the on and off duration times and s is the transition slew.
Degradation models, such as a BTI and HCI models, based on a change in threshold-voltage may be generated using this functional expression.”)
Bansal does not teach
determining model coefficients for the timing model for each of the one or more circuit components based on a circuit simulation
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal does not teach
determining a timing performance of the circuit block by combining timing models of logic stages with a propagation of an output transition time of a successive stage as the input transition time of a next stage
But Bansal discloses
(Bansal, Abstract: “A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. … A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.”)
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
(Bansal, p. 3 [0028] “Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram is illustrated of a diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles.”)
(Bansal, p. 1 [0008] “In accordance with the present principles, a method for estimating delay deterioration in an integrated circuit includes estimating static or statistical degradation over each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit, estimating a static or statistical change in timing delay for each of the one or more lifetimes of each device directly from each of the estimated degradations of the at least one characteristic of each device and performing a static or statistical timing analysis for each of the estimated changes in timing delay to determine static to statistical circuit path delays over each of the one or more lifetimes.”)
(Bansal, p. 5 “The product of this non-linear mapping is a distribution of values of timing delays of that device as a result of the estimated degradation in that device. In block 340, a distribution of values of the output transition time of the device is computed as a function of an input arrival time and the modified timing delays. In block 350, an expected failure probability of the integrated circuit is presented based on a distribution of circuit output times in combination with an expected lifetime and the expected operational frequency of the integrated circuit.”)
Bansal does not teach
estimating an aging related threshold voltage degradation based on a stress simulation of a transistor
But Bansal discloses
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
(Bansal, p. 4 [0040] “In block 250, the degradation of a characteristic in a device is estimated based on the monitored voltages and logical values. As described above, a model may represent degradation as a change in a device's threshold voltage (
∆
V
T
) as a function of operating voltage (
V
d
d
), operating temperature (T), on and off duration times (
t
o
n
and
t
o
f
f
) and transition slew (s) over a plurality of lifetimes.”)
(Bansal, p. 4 [0048] In the case of simulations, the device under consideration may be simulated using a transistor level simulator, such as SPICE, under the device's specific input slew, load and operating conditions, to determine a change in timing delay due to the estimated degradation.”)
(Bansal, p. 4 “The simulation uses a specific pattern representative of a workload to be seen by the integrated circuit defined by the circuit definition.”)
Bansal does not teach
updating the model coefficients based on the aging related threshold voltage degradation, wherein the updating the model coefficients results in an updated aging aware timing model for the one or more circuit components
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal does not teach
updating the timing model for aging related degradation in stacked transistors in a multi-stack circuit
Bansal does not teach
determining an aging stress effect propagation through the one or more circuit components in the circuit block
But Bansal discloses
(Bansal, p. 3 [0028] “Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram is illustrated of a diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles.”)
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Further, RAVI BABU PITTU et. al. (US 20200019663 A1), hereinafter PITTU discloses
(PITTU, p. 2 “It is worth noting that aging effects on a circuit cell, such as a standard cell or a logic gate, in an integrated circuit will vary in response to input stress imposed thereon. “)
Bansal or PITTU do not teach
updating the timing model for multiple stages of transistors of the circuit component based on the aging stress effect propagation
Bansal or PITTU do not teach
determining an aging aware timing performance of the circuit block based on the aging aware timing model of the one or more circuit components in the circuit block
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal or PITTU do not teach
and performing a signal processing operation based on the aging aware timing model.
Regarding claim 12
Bansal discloses
A system for estimating a timing performance of a circuit block, comprising
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
a memory that comprises computer-executable instructions
(Bansal, p. 2 “Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.”)
(Bansal, p. 2 “These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.”)
(Bansal, p. 6 [0072] “As shown in FIG. 5, computer system/server 512 in computing system 500 is shown in the form of a general-purpose computing device. The components of computer system/server 512 may include, but are not limited to, one or more processors or processing units 616, a system memory 528, and a bus 518 that couples various system components including system memory 528 and processing units 516.”)
a processor that executes the computer-executable instructions to perform operations, comprising
(Bansal, p. 2 “These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.”)
Bansal does not teach
determining a timing model for one or more circuit components based on threshold crossing points for each circuit component in a circuit block
But Bansal discloses an inverse of it
(Bansal, p. 3, “A functional expression for a change in threshold-voltage can be expressed as
∆
V
T
=
f
(
V
d
d
,
T
,
t
o
n
,
t
o
f
f
,
S
)
where
V
d
d
is the operating voltage, T is the operating temperature,
t
o
n
and
t
o
f
f
are the on and off duration times and s is the transition slew.
Degradation models, such as a BTI and HCI models, based on a change in threshold-voltage may be generated using this functional expression.”)
Bansal does not teach
determining model coefficients for the timing model for each of the one or more circuit components based on a circuit simulation
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal does not teach
determining a timing performance of the circuit block by combining timing models of logic stages with a propagation of an output transition time of a successive stage as the input transition time of a next stage
Bur Bansal discloses
(Bansal, Abstract: “A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. … A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.”)
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
(Bansal, p. 3 [0028] “Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram is illustrated of a diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles.”)
(Bansal, p. 1 [0008] “In accordance with the present principles, a method for estimating delay deterioration in an integrated circuit includes estimating static or statistical degradation over each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit, estimating a static or statistical change in timing delay for each of the one or more lifetimes of each device directly from each of the estimated degradations of the at least one characteristic of each device and performing a static or statistical timing analysis for each of the estimated changes in timing delay to determine static to statistical circuit path delays over each of the one or more lifetimes.”)
(Bansal, p. 5 “The product of this non-linear mapping is a distribution of values of timing delays of that device as a result of the estimated degradation in that device. In block 340, a distribution of values of the output transition time of the device is computed as a function of an input arrival time and the modified timing delays. In block 350, an expected failure probability of the integrated circuit is presented based on a distribution of circuit output times in combination with an expected lifetime and the expected operational frequency of the integrated circuit.”)
Bansal does not teach
estimating an aging related threshold voltage degradation based on a stress simulation of a transistor
But Bansal discloses
(Bansal, p. 2 [0015] “FIG. 1 is a block/flow diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles;”)
(Bansal, p. 4 [0040] “In block 250, the degradation of a characteristic in a device is estimated based on the monitored voltages and logical values. As described above, a model may represent degradation as a change in a device's threshold voltage (
∆
V
T
) as a function of operating voltage (
V
d
d
), operating temperature (T), on and off duration times (
t
o
n
and
t
o
f
f
) and transition slew (s) over a plurality of lifetimes.”)
(Bansal, p. 4 [0048] In the case of simulations, the device under consideration may be simulated using a transistor level simulator, such as SPICE, under the device's specific input slew, load and operating conditions, to determine a change in timing delay due to the estimated degradation.”)
(Bansal, p. 4 “The simulation uses a specific pattern representative of a workload to be seen by the integrated circuit defined by the circuit definition.”)
Bansal does not teach
updating the model coefficients based on the aging related threshold voltage degradation, wherein the updating the model coefficients results in an updated aging aware timing model for the one or more circuit components
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal does not teach
updating the timing model for aging related degradation in stacked transistors in a multi-stack circuit
Bansal does not teach
determining an aging stress effect propagation through the one or more circuit components in the circuit block
But Bansal discloses
(Bansal, p. 3 [0028] “Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram is illustrated of a diagram of a system/method for determining the impact of aging on timing performance for one or more lifetimes in integrated circuits according to the embodiments of the present principles.”)
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Further, PITTU discloses
(PITTU, p. 2 “It is worth noting that aging effects on a circuit cell, such as a standard cell or a logic gate, in an integrated circuit will vary in response to input stress imposed thereon. “)
Bansal and PITTU does not teach
updating the timing model for multiple stages of transistors of the circuit component based on the aging stress effect propagation
Bansal or PITTU do not teach
determining an aging aware timing performance of the circuit block based on the aging aware timing model of the one or more circuit components in the circuit block
But Bansal discloses
(Bansal, p. 5, [0060] “In one implementation, the stress time (
t
s
), relax time (
t
r
) and operating temperature (T) of the device in question may be directly calculated from the following relationships,
t
s
=
t
s
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
t
r
=
t
r
_
o
r
g
t
s
i
m
_
o
r
g
*
N
e
w
_
L
i
f
e
t
i
m
e
*
1
+
k
0
*
f
o
r
g
f
n
e
w
,
T
=
T
o
r
g
*
k
2
*
V
d
d
_
n
e
w
a
+
k
3
*
exp
V
d
d
,
[0061] where
t
r
_
o
r
g
is the original stress time,
t
r
_
o
r
g
is the original relax time,
t
s
i
m
_
o
r
g
is the original simulation timespan,
f
o
r
g
is the original operating frequency, f.sub.new is the new operating frequency,
T
o
r
g
is the original operating temperature and
V
d
d
_
n
e
w
is the new operating voltage. Also, where a, k0, k2 and k3 are predetermined coefficients.”)
Bansal or PITTU do not teach
and performing a signal processing operation based on the aging aware timing model.
Claims 2-3, 6-7, and 13-14, 17-18, 20 are allowable based on their dependency to claims 1 and 12 respectively, for the reasons stated above.
Claim Rejections - 35 USC § 112
Claims 8 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8
Claim 8 recites the limitation “the stress modeling” in line 1. There is insufficient antecedent basis for this limitation in the claim.
(Changing it to “the stress simulation” will overcome this rejection.)
Regarding claim 19
Claim 19 recites the limitation “the stress modeling” in line 1. There is insufficient antecedent basis for this limitation in the claim.
(Changing it to “the stress simulation” will overcome this rejection.)
Conclusion
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851