Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheon, Sejune, et al. (“Convolutional neural network for wafer surface defect classification and the detection of unknown defect class,” IEEE Transactions on Semiconductor Manufacturing 32.2 (2019): 163-170; hereinafter “Cheon”) in view of Shin, Wooksoo, Hyungu Kahng, and Seoung Bum Kim (“Mixup-based classification of mixed-type defect patterns in wafer bin maps,” Computers & Industrial Engineering 167 (2022): 107996; hereinafter “Shin,” cited by the applicant in an Information Disclosure Statement).
Regarding Claim 1, Cheon teaches a method for training a machine learning model for the automatic detection and classification of defects on wafers (Abstract and section III. A—a convolutional neural network is used for automatic defect classification {ADC} on wafers), comprising:
receiving a plurality of labeled images of individual wafer defects having multiple, respective defect classifications (fig. 4 and section IV. A—a dataset of wafer images is received. The images are of individual wafer defects having multiple classifications, including spot, scratch, and particles, as shown in fig. 4);
creating a first training set comprising the received, plurality of the labeled images of the individual wafer defects having the multiple defect classifications (fig. 4 and sections IV. A and B—a training dataset is created from wafer images and rotated/mirrored versions of the images. The images are of individual wafer defects including spot, scratch, and particles, as shown in fig. 4);
training the machine learning model to automatically detect and classify wafer defects in a first stage using the first training set (section IV. B); and
training the machine learning model to automatically detect and classify wafer defects in a second stage using a second training set (section IV. B—the validation set is a second training set that is used to train the machine learning model).
Cheon does not specifically teach:
blending at least one set of at least two labeled images having different classifications to generate additional labeled image data;
creating a second training set comprising the generated blended, additional labeled image data.
However, Shin teaches:
blending at least one set of at least two labeled images having different classifications to generate additional labeled image data (section 3—the mixup methods blend labeled wafer images to generate additional labeled image data. Section 4.3, under the “Classification accuracy of mixed-type defect patterns” heading, describes generating target labels for the additional image data using the Summation Mixup method);
creating a second training set comprising the generated blended, additional labeled image data (section 3—the blended images are used to create a second training set for model training).
All of the claimed elements were known in Cheon and Shin and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the blending to create a second data set of Shin with the training using a second dataset of Cheon to yield the predictable result of blending at least one set of at least two labeled images having different classifications to generate additional labeled image data; creating a second training set comprising the generated blended, additional labeled image data; and training the machine learning model to automatically detect and classify wafer defects in a second stage using the second training set. One would be motivated to make this combination for the purpose of improving the detection of mixed-type defects when only single-defect data is available (Shin, section 1, last paragraph).
Regarding Claim 6, Cheon teaches a method for the automatic detection and classification of defects on wafers using a trained machine learning model (Abstract and section III. A—a convolutional neural network is used for automatic defect classification {ADC} on wafers), comprising:
receiving at least one unlabeled image of a surface of a wafer (section IV. A—Dataset-UN {unknown} is a set of unlabeled images of a surface of a wafer);
applying the trained machine learning (ML) model to the at least one unlabeled wafer image (section IV. C—the classification results are based on applying the trained ML model to sets of wafer images), the machine learning model having been trained to detect and classify individual defects on wafers using a first set of labeled images of individual wafer defects (section IV. A and B—the ML model is trained on Dataset-TT and modified images generated from Dataset-TT to classify individual defects on wafers. The images are of individual wafer defects including spot, scratch, and particles, as shown in fig. 4); and
determining a respective defect classification for the at least one unlabeled wafer image using the trained machine learning model (section IV. C).
Cheon teaches training the machine learning model using a second set of additional wafer defect images section IV. B—the validation set is a second training set that is used to train the machine learning model), but does not specifically teach a second set of additional wafer defect images generated from at least two labeled images having different classifications being blended.
However, Shin teaches training a machine learning model using a second set of additional wafer defect images generated from at least two labeled images having different classifications being blended (section 3—the mixup methods blend labeled wafer images to generate additional labeled image data, and training the machine learning model using the blended images. Section 4.3, under the “Classification accuracy of mixed-type defect patterns” heading, describes generating target labels for the additional image data using the Summation Mixup method).
All of the claimed elements were known in Cheon and Shin and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the blending to create a second data set of Shin with the training using a second dataset of Cheon to yield the predictable result of applying the trained machine learning (ML) model to the at least one unlabeled wafer image, the machine learning model having been trained to detect and classify individual defects on wafers using a first set of labeled images of individual wafer defects and a second set of additional wafer defect images generated from at least two labeled images having different classifications being blended. One would be motivated to make this combination for the purpose of improving the detection of mixed-type defects when only single-defect data is available (Shin, section 1, last paragraph).
Regarding Claim 11, Cheon teaches an apparatus for training a machine learning model for the automatic detection and classification of defects on wafers (Section I and fig. 1, including ADC system), comprising:
a processor; and a memory having stored therein at least one program, the at least one program including instructions which, when executed by the processor, cause the apparatus to perform a method (fig. 2 and section III. A—the use of a CNN architecture implies a processor executing instructions stored in a memory). Cheon and Shin teach the method comprising the steps of the present claim in the same manner as for claim 1.
Regarding Claim 16, Cheon teaches an apparatus for the automatic detection and classification of defects on wafers using a trained machine learning model (Section I and fig. 1, including ADC system), comprising:
a processor; and a memory having stored therein at least one program, the at least one program including instructions which, when executed by the processor, cause the apparatus to perform a method fig. 2 and section III. A—the use of a CNN architecture implies a processor executing instructions stored in a memory). Cheon and Shin teach the method comprising the steps of the present claim in the same manner as for claim 6.
Regarding Claims 2, 7, 12, and 17, Cheon/Shin teaches wherein the multiple defect classifications comprise at least two of a particle defect, a fiber defect, a stain defect, or no defect (Cheon, fig. 4 and section IV. A—defect classifications include a rock-shaped particle, a ring-shaped particle, and a scratch. Shin, fig. 2 and section 3 also teaches defects including no defect and particle defects).
Regarding Claims 3, 9, 13, and 19, Cheon/Shin teaches wherein the ML model comprises at least one of a vision transformer model, a convolutional neural network model, or a recurrent neural network model (Cheon, section III. A and fig. 3).
Regarding Claims 4, 10, 14, and 20, Cheon/Shin teaches blending the at least one set of the at least two labeled images having different classifications using at least one weighted component (Shin, section 3—images and labels are blended using weights λ).
Regarding Claims 5 and 15, Cheon/Shin teaches wherein the at least one set of the at least two labeled images having different classifications are blended using a mix-up augmentation process (Shin, section 3—the Summation Mixup process is an augmented version of the Original Mixup process, i.e. a mix-up augmentation process).
Regarding Claims 8 and 18, Cheon/Shin teaches determining if the wafer contains a critical defect from the at least one determined defect classification (Shin, section 1—wafers with defects are considered dies that fail, indicating that the defects are critical).
Response to Arguments
Applicant’s arguments with respect to claim have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In view of the applicant’s arguments and the examiner’s discussion with the applicant’s representative, the examiner agrees that Rundo et al. (U.S. 2024/0202908) does not properly teach detecting and classifying individual wafer defects as recited by claims 1, 6, 11, and 16. However, the automatic defect classification (ADC) of Cheon teaches detecting and classifying individual defects on wafers, as detailed above. Shis is still relied on to teach blending different image classifications to generate additional labeled image data used to further train a machine learning model, as also detailed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAL W SCHNEE whose telephone number is (571) 270-1918. The examiner can normally be reached M-F 7:30 a.m. - 6:00 p.m.
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/HAL SCHNEE/Primary Examiner, Art Unit 2129
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