Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-14) in the reply filed on 07/13/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
1. Claims 1, 5-8 and 12-14 are rejected under 35 U.S.C. 103 as obvious over Lam et al. (Patent No.: US 9,646,961 A1) in view of Sarkar et al. (Pub. No. : US 2018/0226331 A1).
Regarding Claim 1, Lam et al. discloses an integrated circuit (IC) structure on a production die, comprising: an active transistor region of electrically functioning transistors on the production die (abstract, Col. 54, L 21-Col. 55, L 28; Figs. 2-4 & 6-8 – all these figures depict standard cell logic section; the ICs include logic cells comprising functioning transistors and fill cells, configured for compatibility with the standard logic cells); a device under test (DUT) cell array in a fill region on the production die (abstract, Col. 54, L 21-Col. 55, L 28; Figs. 1-6 & 44-50 – this prior art teaches fill cells containing device under test (DUT) structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”)), the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die (abstract, Col. 69, L 55-Col. 70, L 40; Figs. 12, 44-50 – teaches fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”); the IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode), the DUT transistor structures comprising one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors (abstract, Col. 58, L 24-Col. 59, L 35; Figs. 7-13 & 41-50 teaches fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode). Lam et al. does not explicitly disclose a guard ring buffer at a transition between the active transistor region and the DUT cell array. However, Sarkar et al. teaches a guard ring buffer at a transition between the active transistor region and the DUT cell array (Par. 0033-0036; Figs. 2-3 – this prior art teaches placing test structures in region 306 which lies between two guard rings 302 and 304; in other words, a guard ring buffer isolates the active transistor region from the DUT cell array)
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Sarker et al. to adapt integrated circuit (IC) structure on a production die, comprising: a guard ring buffer at a transition between the active transistor region and the DUT cell array of Lam et al. in order to make good electrical isolation between DUT and electrically functioning transistors.
Regarding Claim 5, modified Lam et al., as applied to claim 1, discloses the IC structure, wherein the DUT cell array is fabricated on the production die using materials used to fabricate the active transistor region (abstract, Col. 69, L 55-Col. 70, L 40; Figs. 12, 44-50).
Regarding Claim 6, modified Lam et al., as applied to claim 1, discloses the IC structure, wherein the DUT transistor structures are used to identify various types of defects, including trench contact (TCN) opens, via to gate opens (via G), via TCN opens, a poly end-to-end shorts, metal zero end-to-end shorts, metal zero-to-via shorts or a combination thereof (abstract, Col. 9, L 61- Col. 12, L 52; Figs. 14-36 & 44-50).
Regarding Claim 7, modified Lam et al., as applied to claim 1, discloses the IC structure, wherein the DUT transistor structures are standard design rule compatible for layouts and densities (abstract, Col. 2, L 66- Col. 4, L 27; Figs. 44-50).
Regarding Claim 8, Lam et al. discloses an integrated circuit (IC) assembly, comprising:
a circuit board (abstract; Figs. 1-8 - not mentioned explicitly but its presence implied in a complete device involving integrated circuits);
an active transistor region of electrically functioning transistors on the circuit board (abstract, Col. 54, L 21-Col. 55, L 28; Figs. 2-4 & 6-8 – all these figures depict standard cell logic section; the ICs include logic cells comprising functioning transistors and fill cells, configured for compatibility with the standard logic cells); a device under test (DUT) cell array in a fill region adjacent to the active transistor region (abstract, Col. 54, L 21-Col. 55, L 28; Figs. 1-6 & 44-50 – this prior art teaches fill cells containing device under test (DUT) structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”)), the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens (abstract, Col. 69, L 55-Col. 70, L 40; Figs. 12, 44-50 – teaches fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”); the IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode), the DUT transistor structures comprising one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors (abstract, Col. 58, L 24-Col. 59, L 35; Figs. 7-13 & 41-50 teaches fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode). Lam et al. does not explicitly disclose a guard ring buffer at a transition between the active transistor region and the DUT cell array. However, Sarkar et al. teaches a guard ring buffer at a transition between the active transistor region and the DUT cell array (Par. 0033-0036; Figs. 2-3 – this prior art teaches placing test structures in region 306 which lies between two guard rings 302 and 304; in other words, a guard ring buffer isolates the active transistor region from the DUT cell array)
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Sarker et al. to adapt integrated circuit (IC) structure on a production die, comprising: a guard ring buffer at a transition between the active transistor region and the DUT cell array of Lam et al. in order to make good electrical isolation between DUT and electrically functioning transistors.
Regarding Claim 12, modified Lam et al., as applied to claim 8, discloses the IC structure, wherein the DUT cell array is fabricated using materials used to fabricate the active transistor region (abstract, Col. 69, L 55-Col. 70, L 40; Figs. 12, 44-50).
Regarding Claim 13, modified Lam et al., as applied to claim 8, discloses the IC structure, wherein the DUT transistor structures are used to identify various types of defects, including trench contact (TCN) opens, via to gate opens (via G), via TCN opens, a poly end-to-end shorts, metal zero end-to-end shorts, metal zero-to-via shorts or a combination thereof (abstract, Col. 9, L 61- Col. 12, L 52; Figs. 14-36 & 44-50).
Regarding Claim 14, modified Lam et al., as applied to claim 8, discloses the IC structure, wherein the DUT transistor structures are standard design rule compatible for layouts and densities (abstract, Col. 2, L 66- Col. 4, L 27; Figs. 44-50).
1. Claims 2-4 and 9-11 are rejected under 35 U.S.C. 103 as obvious over Lam et al. (Patent No.: US 9,646,961 A1) and Sarkar et al. (Pub. No. : US 2018/0226331 A1), as applied to claims 1 and 8.
Regarding Claim 2, modified Lam et al., as applied to claim 1, does not explicitly disclose the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array. However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer at least a partially surrounds the active transistor region (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region which is in contrast to the limitation of this claim which recites the guard ring buffer to surround the DUT cell array instead. However, in both cases, effective isolation is ensured between the active transistor region and the DUT cell array. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array. It would have been an obvious matter of design choice to adapt the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array, since applicant has not disclosed that the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the IC structure, wherein the guard ring buffer at least a partially surrounds the active transistor region .Furthermore, it has been held that choosing from a finite number of identified, predictable solutions, guard ring buffer either surrounding the DUT cell array or the active transistor region, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007). Additionally, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Regarding Claim 3, modified Lam et al., as applied to claim 1, does not explicitly disclose the IC structure, wherein the guard ring buffer surrounds the DUT cell array. However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region which is in contrast to the limitation of this claim which recites the guard ring buffer to surround the DUT cell array instead. However, in both cases, effective isolation is ensured between the active transistor region and the DUT cell array. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer surrounds the DUT cell array. It would have been an obvious matter of design choice to adapt the IC structure, wherein the guard ring buffer surrounds the DUT cell array, since applicant has not disclosed that the IC structure, wherein the guard ring buffer surrounds the DUT cell array solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the IC structure, wherein the guard ring buffer surrounds the active transistor region. Furthermore, it has been held that choosing from a finite number of identified, predictable solutions, guard ring buffer either surrounding the DUT cell array or the active transistor region, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007). Additionally, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Regarding Claim 4, modified Lam et al., as applied to claim 1, does not explicitly disclose the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches. However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer has certain width (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer has certain width. However, it does not explicitly disclose the guard ring buffer has a width of approximately 3-5 poly pitches. It is understood that the width of the guard ring buffer is a result-effective variable. If the width is too thin, the isolation might be less than perfect. If the width is too thick, on the other hand, it might not be the best use of available space. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 9, modified Lam et al., as applied to claim 8, does not explicitly disclose the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array. However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer at least a partially surrounds the active transistor region (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region which is in contrast to the limitation of this claim which recites the guard ring buffer to surround the DUT cell array instead. However, in both cases, effective isolation is ensured between the active transistor region and the DUT cell array. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array. It would have been an obvious matter of design choice to adapt the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array, since applicant has not disclosed that the IC structure, wherein the guard ring buffer at least a partially surrounds the DUT cell array solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the IC structure, wherein the guard ring buffer at least a partially surrounds the active transistor region .Furthermore, it has been held that choosing from a finite number of identified, predictable solutions, guard ring buffer either surrounding the DUT cell array or the active transistor region, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007). Additionally, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Regarding Claim 10, modified Lam et al., as applied to claim 8, does not explicitly disclose the IC structure, wherein the guard ring buffer surrounds the DUT cell array However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer surrounds the active transistor region which is in contrast to the limitation of this claim which recites the guard ring buffer to surround the DUT cell array instead. However, in both cases, effective isolation is ensured between the active transistor region and the DUT cell array. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer surrounds the DUT cell array. It would have been an obvious matter of design choice to adapt the IC structure, wherein the guard ring buffer surrounds the DUT cell array, since applicant has not disclosed that the IC structure, wherein the guard ring buffer surrounds the DUT cell array solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the IC structure, wherein the guard ring buffer surrounds the active transistor region. Furthermore, it has been held that choosing from a finite number of identified, predictable solutions, guard ring buffer either surrounding the DUT cell array or the active transistor region, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007). Additionally, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Regarding Claim 11, modified Lam et al., as applied to claim 8, does not explicitly disclose the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches. However, modified Lam et al. discloses the IC structure, wherein the guard ring buffer has certain width (Sarker - Par. 0033-0036; Figs. 2-3). In summary, modified Lam et al. discloses the IC structure, wherein the guard ring buffer has certain width. However, it does not explicitly disclose the guard ring buffer has a width of approximately 3-5 poly pitches. It is understood that the width of the guard ring buffer is a result-effective variable. If the width is too thin, the isolation might be less than perfect. If the width is too thick, on the other hand, it might not be the best use of available space. Modified Lam et al. discloses the claimed invention except for the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the IC structure, wherein the guard ring buffer has a width of approximately 3-5 poly pitches., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lam et al. (Patent No.: US 9,748,153 B1) – This prior art teaches n integrated circuit (IC) structure on a production die, comprising: an active transistor region of electrically functioning transistors on the production die; a device under test (DUT) cell array in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die, the DUT transistor structures comprising one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors; Figs. 1-17 and 44-50)
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08/01/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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