DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to because the width of each opening 18 (specifically shown in Figure 1) is labeled as “w2” whereas the same width is referenced as “w1” in paragraphs [0054], [0064], and [0069], of the instant Specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, 11, and 13, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwamoto (US 20110203839 A1), hereinafter referred to as “Iwamoto”;
[Ishii et al. (US 20170025318 A1), hereinafter referred to as “Ishii” is utilized herein as evidence].
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Regarding claim 1, Iwamoto discloses an electronic device (fig. 1, 1; see [0021]) comprising:
an electrically-insulating and highly thermal conductive sheet (see figs. 1-3; layers 11-13 comprise an electrically-insulating and highly thermal conductive sheet; see [0036]) having a first surface (see figs. 1-3; the first surface is the exposed bottom surface of buffer layer 13) and a second surface (see figs. 1-3; the second surface is the exposed top surface of buffer layer 12) opposite the first surface, wherein the electrically-insulating and highly thermal conductive sheet is a perforated stack (see fig. 3 and via holes 14) of a thermal conductive material-containing layer (figs. 1-3, 11; see [0023]) sandwiched between a first ceramic layer (figs. 1-3, 12; see [0024] and [0026]; buffer layer 12 is composed of either PZT (lead zirconate titanate) or BST (Barium Strontium Titanate) which are both ceramic materials) and a second ceramic layer (figs. 1-3, 13; see [0024] and [0026]; buffer layer 13 is composed of either PZT (lead zirconate titanate) or BST (Barium Strontium Titanate) which are both ceramic materials);
a packaging substrate (fig. 1, 31; see [0033] then [0030]) located on the first surface of the electrically-insulating and highly thermal conductive sheet;
and at least one semiconductor chip (fig. 1, 40; see [0035]) located on the second surface of the electrically- insulating and highly thermal conductive sheet.
Regarding claim 2, Iwamoto discloses the electronic device of Claim 1, wherein the electrically-insulating and highly thermal conductive sheet (figs. 1-3, layers 11-13; see [0036]) has a plurality of openings (fig. 3, 14) that extend from the first surface (see figs. 1-3; the first surface is the exposed bottom surface of buffer layer 13) of the electrically-insulating and highly thermal conductive sheet to the second surface (see figs. 1-3; the second surface is the exposed top surface of buffer layer 12) of the electrically-insulating and highly thermal conductive sheet.
Regarding claim 3, Iwamoto discloses the electronic device of Claim 2, wherein each of the openings (fig. 3, 14) is filled with solder (fig. 1, 16; c.f. fig. 5; see [0039] then [0028]: via 16 is composed of tin;
see evidentiary reference Ishii [0064]: solder (specifically lead-free solder which is referenced in paragraph [0067] of applicant’s Specification) can be composed solely of tin).
Regarding claim 4, Iwamoto discloses the electronic device of Claim 2, wherein each of the openings (fig. 3, 14) is filled with an electrically conductive metal or an electrically conductive metal alloy (fig. 1, 16; c.f. fig. 5; see [0039] then [0028]: via 16 is composed of tin).
Regarding claim 5, Iwamoto discloses the electronic device of Claim 1, wherein the first ceramic layer (figs. 1-3, 12; see [0024] and [0026]) and the second ceramic layer (figs. 1-3, 13; see [0024] and [0026]) are both composed of a same electrically insulating, yet thermally conductive, material (see [0024] and [0026]: buffer layers 12 and 13 are both composed of PZT).
Regarding claim 6, Iwamoto discloses the electronic device of Claim 1, wherein the first ceramic layer (figs. 1-3, 12; see [0024] and [0026]) and the second ceramic layer (figs. 1-3, 13; see [0024] and [0026]) are both composed of different electrically insulating, yet thermally conductive, material (see [0024] and [0026]: buffer layer 12 is composed of PZT while buffer layer 13 is composed of BST).
Regarding claim 7, Iwamoto discloses the electronic device of Claim 1, wherein the thermal conductive material-containing layer (figs. 1-3, 11) is composed of an electrically conductive metal, electrically conductive metal alloy or graphite (see [0023]: metal core substrate 11 is composed of copper (Cu)).
Regarding claim 9, Iwamoto discloses the electronic device of Claim 1, further comprising a dielectric coating (fig. 1, 15; c.f. fig. 4; see [0027]) surrounding the perforated stack.
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Regarding claim 11, Iwamoto discloses the electronic device of Claim 2, further comprising first metal bond pads (fig. 1, 34; see [0033]) located on the packaging substrate and second metal bond pads (fig. 1, 24; see [0031]; also see [0034] and note that wire 24 is mechanically fixed and electrically connected to electronic device 40 through bumps 41) located on the semiconductor chip, wherein portions of the first metal bond pads and portions of the second metal bond pads are aligned with each of the openings (see fig. 1 and c.f. fig. 4: vias 16 are disposed in via holes 14a which are openings in the substrate (i.e. elements 11-13); portions of both wire 24 and wire 34 are aligned with each of the vias 16).
Regarding claim 13, Iwamoto discloses the electronic device of Claim 1, wherein the packaging substrate (fig. 1, 31) comprises a laminate, an organic interposer, a silicon interposer o r a glass interposer (see [0033] then [0030]: insulating layer 31 comprises polypropylene which is an organic material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Song et al. (CN 105762266 A), hereinafter referred to as “Song” (please note that all citations to Song reference the PDF copy of Song included with this Office Action).
Iwamoto discloses the electronic device of Claim 1, wherein the thermal conductive material-containing layer (Iwamoto figs. 1-3, 11) is composed of copper (Cu) (see Iwamoto [0023]: metal core substrate 11 is composed of copper (Cu)).
Iwamoto fails to disclose wherein the first ceramic layer and the second ceramic layer are both composed of aluminum nitride (AlN).
Song discloses a semiconductor device (see Song fig. 1 and page 3, lines 19-20) with an electrically-insulating and highly thermal conductive sheet (Song fig. 1, 200; see page 4, lines 6-18) for dissipating heat from a semiconductor component (Song fig. 1, 300; see page 3, lines 33-38), wherein the electrically-insulating and highly thermal conductive sheet comprises an alternating stack of aluminum nitride (AlN) ceramic layers (Song fig. 1, 210; see page 4, line 7) and thermal conductive graphene particle layers (i.e. thermal conductive material-containing layers) (Song page 1, 220; see page 4, lines 19-20).
The alternating aluminum nitride layers of Song are incorporated as the first and second ceramic layers of the device of Iwamoto wherein the combination discloses wherein the first ceramic layer and the second ceramic layer are both composed of aluminum nitride (AlN), and the thermal conductive material-containing layer is composed of copper (Cu).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the aluminum nitride layers of Song because the combination is a simple substitution of one known ceramic material for another to obtain predictable results—simple substitution of the PZT and/or BST ceramic layers of Iwamoto (Iwamoto figs. 1-3, 12 and 13; see [0024] and [0026]) with the aluminum nitride ceramic layers of Song (Song fig. 1, 210) in order to obtain predictable results (the electrically insulative, mechanically supportive, and protective properties of aluminum nitride are predictable and well known in the art).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Mori et al. (US 20050012217 A1), hereinafter referred to as “Mori”, further in view of Chou et al. (US 20200388564 A1), hereinafter referred to as “Chou”.
Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to disclose the electronic device further comprising a first non-conductive adhesive layer contacting the first ceramic layer and a portion of the packaging substrate, and a second non-conductive adhesive layer contacting the second ceramic layer and a portion of the semiconductor chip.
Mori discloses an electronic device (Mori fig. 2, 1) comprising a core board (Mori fig. 2, 2; c.f. fig. 1; see [0058]) on a packaging substrate (More fig. 2, 3; c.f. fig. 1; see [0071]), wherein the wiring substrate is a ceramic layer (see Mori [0060]), and wherein the device further comprises a first non-conductive adhesive layer (Mori fig. 2, 9b; see [0071]: insulating layer 9b is polyimide resin) contacting the wiring substrate and a portion of the packaging substrate (see Mori fig. 2; insulating layer 9b contacts a portion of buildup wiring layer 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the first non-conductive adhesive layer of Mori (using it to adhere the electrically-insulating and highly thermal conductive sheet (including the first ceramic layer) to the packaging substrate) in order to increase manufacturing yield and quality (see Mori [0071]: insulating layer 9b is specifically heat-curable at or below the solder reflow temperature (cited as 250 degrees Celsius); this property enables insulating layer 9b to be flowed and cured without disrupting previously deposited solder which would, in turn, increase manufacturing yield and quality).
Chou discloses an electronic device (Chou fig. 2E, 4; see [0026]) comprising a semiconductor chip (Chou fig. 2E, 40; see [0043]) mounted on an interposer (Chou fig. 2E, 2a; see [0028]), wherein the electronic device further comprises a second non-conductive adhesive layer (Chou fig. 2E, 41; see [0044]: encapsulation layer 41 is polyimide resin) contacting the interposer and a portion of the semiconductor chip.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Iwamoto and Mori with the second non-conductive adhesive layer of Chou (using it to adhere the electrically-insulating and highly thermal conductive sheet (including the second ceramic layer) to the semiconductor chip) in order to protect the bottom of the semiconductor chip from mechanical abrasion and foreign contaminants.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Furutani et al. (US 20130081866 A1), hereinafter referred to as “Furutani”.
Iwamoto discloses the electronic device of Claim 11.
Iwamoto fails to explicitly disclose the electronic device further comprising a first solder layer located on each of the first metal bond pads and a second solder layer located on each of the second metal bond pads, wherein the first metal bond pads, the first solder layer, the second metal bond pads and the second solder layer are aligned with each of the openings.
Furutani discloses a printed wiring board for an electronic device (Furutani fig. 9, 10; see [0065]) comprising a first solder layer (Furutani fig. 9, 76D; see [0029]) located on a portion of each of a plurality of first metal bond pads (Furutani fig. 9, 60B; c.f. fig. 6; see [0028]) and a second solder layer (Furutani fig. 9, 76U; see [0029]) located on a portion of each of a plurality of second metal bond pads (Furutani fig. 9, 60A; see [0027]), wherein the first metal bond pads, the first solder layer, the second metal bond pads and the second solder layer are aligned with each of a plurality of openings (see Furutani fig. 9 and c.f. fig. 1A-E; see [0026]: through-hole conductors 36 are filled in penetrating holes 31 within core substrate 30 (c.f. fig. 9 and [0065]); at least a portion of each of the first and second solder layers and the first and second metal bond pods are aligned with each of the through-hole conductors 36).
The first and second solder layers of Furutani are incorporated into the device of Iwamoto wherein the combination discloses all of the limitations of claim 12.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the first and second solder layers of Furutani to reduce electrical resistance (vertically aligning the conductive path through the electrically-insulating and highly thermal conductive sheet in the combined device reduces the signal distance (and thus the electrical resistance) between the semiconductor chip and the packaging substrate).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Bachman et al. (US 20120020028 A1), hereinafter referred to as “Bachman”.
Regarding claim 14, Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to disclose wherein the semiconductor chip comprises a plurality of stacked semiconductor chips.
Bachman discloses an electronic device (Bachman fig. 1, 100; see [0015]) comprising a plurality of stacked semiconductor chips (Bachman fig. 1, 103 and 106; see [0015] and [0017]) wherein each stacked chip of the plurality is spaced apart by an electrically-insulating and highly thermal conductive sheet (Bachman fig. 1, 160; see [0019]; also see fig. 4I showing a possible embodiment of the heat spreader 160; see [0038]).
The plurality of stacked semiconductor chips of Bachman is incorporated as the semiconductor chip of Iwamoto wherein the combination discloses wherein the semiconductor chip comprises a plurality of stacked semiconductor chips.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the plurality of stacked semiconductor chips of Bachman to increase the processing power and/or memory storage capacity of the device (depending on the specific type of semiconductor chips used).
Regarding claim 15, the previous combined device of Iwamoto and Bachman disclose the electronic device of Claim 14, wherein the plurality of stacked semiconductor chips (Bachman fig. 1, 103 and 106) is located on the electrically-insulating and highly thermal conductive sheet (see Iwamoto figs. 1-3; layers 11-13 comprise an electrically-insulating and highly thermal conductive sheet; see [0036]) comprising a perforated stack (see Iwamoto fig. 3) of a thermal conductive material-containing layer (Iwamoto figs. 1-3, 11; see [0023]) sandwiched between a first ceramic layer (Iwamoto figs. 1-3, 12; see [0024] and [0026]) and a second ceramic layer (Iwamoto figs. 1-3, 13; see [0024] and [0026]).
The previous combined device of Iwamoto and Bachman fails to explicitly disclose the electronic device of Claim 14, wherein each stacked chip of the plurality is spaced apart by another electrically-insulating and highly thermal conductive sheet, wherein the another electrically-insulating and highly thermal conductive sheet is another perforated stack of another thermal conductive material-containing layer sandwiched between another first ceramic layer and another second ceramic layer.
Bachman discloses an electronic device (Bachman fig. 1, 100; see [0015]) comprising a plurality of stacked semiconductor chips (Bachman fig. 1, 103 and 106; see [0015] and [0017]) wherein each stacked chip of the plurality is spaced apart by an electrically-insulating and highly thermal conductive sheet (Bachman fig. 1, 160; see [0019]; also see fig. 4I showing a possible embodiment of the heat spreader 160; see [0038]).
The electrically-insulating and highly thermal conductive sheet (located between the stacked chips) as taught by Bachman is replaced by the electrically-insulating and highly thermal conductive sheet as taught by Iwamoto (and utilized in the previous combined device of Iwamoto and Bachman) wherein the present combination discloses all of the limitations of claim 15.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the previous combined device of Iwamoto and Bachman by inserting the electrically-insulating and highly thermal conductive sheet as taught by Iwamoto between each chip in the plurality of stacked semiconductor chips because the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of the thermal conductive sheet of Bachman (Bachman fig. 1, 160) with the thermal conductive sheet of Iwamoto (see Iwamoto figs. 1-3; layers 11-13 comprise an electrically-insulating and highly thermal conductive sheet) to obtain predicable results (i.e. enhanced heat dissipation between the stacked semiconductor chips; also note the use of the thermal conductive sheet of Iwamoto between the stacked semiconductor chips in the combined device would reduce manufacturing complexity).
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Li (US 20170162517 A1), hereinafter referred to as “Li”.
Regarding claim 16, Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to disclose the device further comprising a lid located on top of the semiconductor chip.
Li discloses an electronic device (Li fig. 2, 1) comprising a lid (Li fig. 2, 160; see [0028]) located on top of a semiconductor chip (Li fig. 2, 145; see [0028]).
The lid of Li is incorporated into the device of Iwamoto wherein the combination discloses all of the limitations of claim 16.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the lid of Li to protect the semiconductor device from foreign contaminants and mechanical damage.
Regarding claim 17, the combined device of Iwamoto and Li discloses the electronic device of Claim 16, wherein the lid (Li fig. 2, 160) is composed of a thermal spreader material (see Li [0028]: “metal back plate (160), which is made from metal or other high thermal conductivity material”).
Regarding claim 19, Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to explicitly disclose wherein the semiconductor chip is a high power semiconductor chip.
Li discloses an electronic device (Li fig. 2, 1) comprising a high power semiconductor chip (Li fig. 2, 140; see [0028]).
The high power semiconductor chip of Li is incorporated as the semiconductor chip in the device of Iwamoto wherein the combination discloses all of the limitations of claim 19.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the high power semiconductor chip of Li to increase the processing power of the device.
Regarding claim 20, Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to explicitly disclose wherein the semiconductor chip is a low power semiconductor chip.
Li discloses an electronic device (Li fig. 2, 1) comprising a low power semiconductor chip (Li fig. 2, 145; see [0028]).
The low power semiconductor chip of Li is incorporated as the semiconductor chip in the device of Iwamoto wherein the combination discloses all of the limitations of claim 20.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the low power semiconductor chip of Li to reduce the thermal output of the device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, in view of Hortaleza (US 20040012078 A1), hereinafter referred to as “Hortaleza”.
Iwamoto discloses the electronic device of Claim 1.
Iwamoto fails to explicitly disclose wherein the electrically-insulating and highly thermal conductive sheet comprises from 50 to 90 percent of the thermal conductive material- containing layer and the remainder of the electrically-insulating and highly thermal conductive sheet, up to 100 percent, comprises from 10 to 50 percent of the first ceramic layer and the second ceramic layer.
Hortaleza discloses an electrically-insulating and highly thermal conductive sheet (see Hortaleza fig. 8; the electrically-insulating and highly thermal conductive sheet comprises rigid core 820 sandwiched by stress absorbing material layers 830 and 831; see [0050] then [0047]: we can conclude that rigid core 820 is a heat spreader and, thus, thermally conductive; c.f. fig. 6 and [0045]) within an electronic device (see Hortaleza fig. 8), the sheet comprising 50 to 90 percent of a thermal conductive material- containing layer (Hortaleza fig. 8, 820; rigid core 820 comprises 50 percent or more of the sheet) and the remainder of the electrically-insulating and highly thermal conductive sheet, up to 100 percent, comprises from 10 to 50 percent of the first material layer (Hortaleza fig. 8, 831) and the second material layer (Hortaleza fig. 8, 830; note that both of the stress-absorbing layers 830 and 831 comprise 50 percent or less of the sheet).
The specific proportions of material layers in an electrically-insulating and highly thermal conductive sheet as taught in Hortaleza is incorporated into the device of Iwamoto wherein thew combination discloses wherein the electrically-insulating and highly thermal conductive sheet comprises from 50 to 90 percent of the thermal conductive material- containing layer and the remainder of the electrically-insulating and highly thermal conductive sheet, up to 100 percent, comprises from 10 to 50 percent of the first ceramic layer and the second ceramic layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwamoto with the aforementioned teachings of Hortaleza to increase the rate of heat dissipation in the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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