DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 29 December 2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 28 August 2025 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13, in line 20, recites “the fourth via laterally spaced apart from the.” The recitation is unclear and indefinite because it appears to be incomplete. For compact prosecution, it will be interpreted as “the fourth via laterally spaced apart from the silicon die.”
Claims 14-17, which depend either directly or indirectly from independent claim 13, do not remedy the issues of claim 13 and therefore are also rejected.
Claim 18, in the last three lines, recites “to provide vertical power distribution through the interconnect bridge through the embedded multi-die interconnect bridge.” First, the recitation “the interconnect bridge” lacks antecedent basis. It is unclear and indefinite as to whether the “interconnect bridge” is the same or different from the “embedded multi-die interconnect bridge. Second, it is unclear and indefinite as to what is meant by the recitation “through the interconnect bridge through the embedded multi-die interconnect bridge.” For compact prosecution, it will be interpreted as “to provide vertical power distribution through the embedded multi-die interconnect bridge.”
Claims 19 and 20, which depend either directly or indirectly from independent claim 18, do not remedy the issues of claim 18 and therefore are also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8, 9, 13, 14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2018/0102311) in view of Yang et al. (U.S. Pub. 2010/0081236) in view of Liu et al. (U.S. Pub. 2015/0028486) in view of Pyo et al. (U.S. Pub. 2018/0175001).
Claim 1: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 41, 49, 56, 59 and 60, comprising:
an interconnect bridge (101) having a first contact pad and a second contact pad thereon, the interconnect bridge (101) comprising a silicon die, wherein the interconnect bridge (101) is over a conductor (uppermost layer of 714);
a second dielectric layer (202 and 550) on the interconnect bridge (101), the second dielectric layer (202 and 550) over the conductor (uppermost layer of 714);
a first via in the second dielectric layer (202 and 550), the first via coupled to the first contact pad;
a second via in the second dielectric layer (202 and 550), the second via coupled to the second contact pad,
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to a fourth via (lower portion of 510), the fourth via (lower portion of 510) laterally spaced apart from the interconnect bridge (101);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductor (uppermost layer of 714);
a first conductive trace in the third dielectric layer (912), the first conductive trace coupled to the first via;
a second conductive trace in the third dielectric layer (912), the second conductive trace coupled to the second via;
a third conductive trace in the third dielectric layer (912), the third conductive trace coupled to the third via (upper portion of 510);
a fifth via in the third dielectric layer (912), the fifth via coupled to the first conductive trace;
a sixth via in the third dielectric layer (912), the sixth via coupled to the second conductive trace;
a seventh via in the third dielectric layer (912), the seventh via coupled to the third conductive trace;
a first die (11) over the third dielectric layer (912), the first die (11) over the interconnect bridge (101) and over the conductor (uppermost layer of 714), and the first die (11) coupled to the fifth via and to the sixth via and to the seventh via; and
a second die (12) over and coupled to the interconnect bridge (101),
wherein the conductor (uppermost layer of 714) is to receive a power supply voltage signal.
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Shih appears not to explicitly disclose an adhesive layer vertically between the interconnect bridge and the conductor, the adhesive layer in contact with the silicon die of the interconnect bridge.
Yang et al., however, discloses, in Fig. 16 and in paragraphs 92 and 95, an adhesive layer (31) vertically between the interconnect bridge (10’) and the conductor (23), the adhesive layer in contact with the silicon die of the interconnect bridge.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Yang et al. to have made an adhesive layer vertically between the interconnect bridge and the conductor, the adhesive layer in contact with the silicon die of the interconnect bridge in order to better secure the interconnect bridge to the underlying layer.
Shih also appears not to explicitly disclose a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent the adhesive layer;
the second dielectric layer on the first dielectric layer; and
the fourth via in the first dielectric layer.
Liu et al., however, discloses, in Figs. 3a-3i and in paragraphs 22, 32, 35, 36, 39, 40 and 46, a first dielectric layer (104a in N-2), the first dielectric layer (104a in N-2) laterally adjacent the interconnect bridge (105), and the first dielectric layer (104a in N-2) laterally adjacent the adhesive layer (105b);
the second dielectric layer (104a in N-1) on the first dielectric layer (104a in N-2); and
the fourth via (104c) in the first dielectric layer (104a in N-2) in order to route electrical signal to different parts of the package.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent the adhesive layer;
the second dielectric layer on the first dielectric layer; and
the fourth via in the first dielectric layer, in order to route electrical signal to different parts of the package (paragraph 22 of Liu et al.).
Shih also appears not to explicitly disclose wherein the conductor is to receive a power supply voltage signal to provide vertical power distribution through the interconnect bridge.
Pyo et al., however, in Fig. 5 and in paragraph 46, discloses the conductor (140 below 200) is to receive a power supply voltage signal to provide vertical power distribution through the interconnect bridge (220).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Pyo et al. that is in the same field of endeavor with Shim et al., before the effective filing date of the claimed invention in order to substitute the conductor is to receive a power supply voltage signal to provide vertical power distribution through the interconnect bridge as disclosed by Pyo et al. for power distribution disclosed by Shim et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the conductor is to receive a power supply voltage signal to provide vertical power distribution through the interconnect bridge disclosed by Pyo et al. for the power distribution disclosed by Shim et al. would have yielded predictable results, namely providing a suitable power supply to the first die and the second die. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 2: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1, and Shih further discloses, in paragraph 60, wherein the second die (12) is coupled to the first die (11) by the interconnect bridge (101).
Claim 3: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1.
Liu et al. further discloses, in Figs. 3a-3i and in paragraph 32, further discloses the first dielectric layer (104a in N-2) is in contact with the conductor (104b).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al., as applied to claim 1, with the further disclosure of Liu et al. to have made the first dielectric layer is in contact with the conductor in order to protect the surrounding elements.
Claim 5: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1.
Since Shih discloses, in Fig. 14 and paragraph 41, a fourth dielectric layer (712) below the second dielectric layer (202 and 550) and the interconnect bridge (101), and Liu et al. discloses, in Fig. 3i, the first dielectric layer (104a in N-2) is under the second dielectric layer (104a in N-1) and adjacent the interconnect bridge (105), Shih in view of Liu et al. would disclose a fourth dielectric layer below the first dielectric layer.
Claim 6: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1, and Shih further discloses, in Fig. 14, wherein the conductor (uppermost layer of 714) comprises multiple regions that are electrically isolated from one another.
Claim 8: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 6, and Shih further discloses, in paragraph 61, wherein the conductor (uppermost layer of 714) is to receive a data signal.
Claim 9: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1, and Shih further discloses, in Fig. 14 and paragraph 38, comprising:
one or more through silicon vias (110) in the silicon die of the interconnect bridge (101).
Claim 13: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 41, 49, 56, 59 and 60, comprising:
a silicon die (101) having a first contact pad and a second contact pad thereon, the silicon die (101) over a backside conductor (uppermost layer of 714);
a second dielectric (202 and 550) on the silicon die (101), the second dielectric (202 and 550) over the backside conductor (uppermost layer of 714);
a first conductive via, a second conductive via, and a third conductive via (upper portion of 510) in the second dielectric (202 and 550), the first conductive via coupled to the first contact pad, the second conductive via coupled to the second contact pad, and the third conductive via (upper portion of 510) coupled to a fourth conductive via (lower portion of 510);
a third dielectric (912) on the second dielectric (202 and 550), the third dielectric over (912) the silicon die (101) and over the backside conductor (uppermost layer of 714);
a first conductor and a second conductor in the third dielectric (912), the first conductor coupled to the first conductive via, and the second conductor coupled to the second conductive via;
a third conductor in the third dielectric (912), the third conductor above and coupled to the third conductive via (upper portion of 510), the fourth via (lower portion of 510) laterally spaced apart from the silicon die;
a fifth conductive via, a sixth conductive via, and a seventh conductive via in the third dielectric (912), the fifth conductive via coupled to the first conductor, the sixth conductive via coupled to the second conductor, and the seventh conductive via coupled to the third conductor;
a main die (11) over the third dielectric (912), the main die (11) over the silicon die (101) and over the conductor (uppermost layer of 714), and the main die (11) coupled to the fifth conductive via and to the sixth conductive via and to the seventh conductive via; and
a second die (12) over and coupled to the silicon die (101);
wherein the backside conductor (uppermost layer of 714) is to receive a power supply voltage.
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Shih appears not to explicitly disclose a non-conductive intervening layer vertically between the silicon die and the backside conductor, the non-conductive intervening layer in contact with the silicon die.
Yang et al., however, discloses, in Fig. 16 and in paragraphs 60, 92 and 95, a non-conductive intervening layer (31) vertically between the silicon die (10’) and the backside conductor (23), the non-conductive intervening layer in contact with the silicon die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Yang et al. to have made a non-conductive intervening layer vertically between the silicon die and the backside conductor, the non-conductive intervening layer in contact with the silicon die in order to better secure the silicon die to the underlying layer. The two elements cited in Shih and Yang merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Shih also appears not to explicitly disclose a first dielectric laterally adjacent the silicon die and laterally adjacent the non-conductive intervening layer;
a second dielectric on the first dielectric and on the silicon die, and
the fourth conductive via in the first dielectric.
Liu et al., however, discloses, in Figs. 3a-3i and in paragraphs 22, 32, 35, 36, 39, 40 and 46, a first dielectric (104a in N-2) laterally adjacent the silicon die (105) and laterally adjacent the intervening layer (105b);
the second dielectric (104a in N-1) on the first dielectric (104a in N-2); and
the fourth conductive via (104c) in the first dielectric (104a in N-2) in order to route electrical signal to different parts of the package.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made a first dielectric laterally adjacent the silicon die and laterally adjacent the non-conductive intervening layer;
a second dielectric on the first dielectric and on the silicon die
the fourth conductive via in the first dielectric in order to route electrical signal to different parts of the package (paragraph 22 of Liu et al.). The elements cited in Shih, Yang, and Liu merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Shih also appears not to explicitly disclose wherein the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the silicon die.
Pyo et al., however, in Fig. 5 and in paragraph 46, discloses the backside conductor (140 below 200) is to receive a power supply voltage signal to provide vertical power distribution through the die (220).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Pyo et al. that is in the same field of endeavor with Shim et al., before the effective filing date of the claimed invention in order to substitute the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the die as disclosed by Pyo et al. for power distribution disclosed by Shim et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the die disclosed by Pyo et al. for the power distribution disclosed by Shim et al. would have yielded predictable results, namely providing a suitable power supply to the main die and the second die. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 14: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 13, and Shih further discloses, in paragraph 60, wherein the second die (12) is coupled to the main die (11) by the silicon die (101).
Claim 16: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 13.
Since Shih discloses, in Fig. 14 and paragraph 41, a fourth dielectric (712) below the second dielectric (202 and 550) and the silicon die (101), and Liu et al. discloses, in Fig. 3i, the first dielectric (104a in N-2) is under the second dielectric (104a in N-1) and adjacent the silicon bridge (105), Shih in view of Liu et al. would disclose a fourth dielectric below the first dielectric.
Claim 17: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 13, and Shih further discloses, in Fig. 14, wherein the backside conductor (uppermost layer of 714) comprises multiple regions that are electrically isolated from one another.
Claim(s) 4, 10-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. as applied to claims 1 and 13 above, and further in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Claim 4: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1.
Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, discloses, in Fig. 6 and in paragraphs 49 and 62, the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch et al.).
Claim 10: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1.
Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. appears not to explicitly disclose further comprising:
a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, discloses, in Fig. 6 and in paragraphs 49 and 62, a cavity (615) laterally between the interconnect bridge (510) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch et al.).
Claims 11 and 12: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 1.
Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die, and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, discloses, in paragraph 74, the first die (1120) is a main die, and the second die (1130) is a secondary die, and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die, and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order for the package to have functionality.
Claim 15: Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. discloses the multi-chip package of claim 13, and Liu et al. further discloses, in Fig. 3g, wherein the first dielectric (104a in N-2) is in contact with the backside conductor (104b).
Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. appears not to explicitly disclose wherein the silicon die is laterally spaced apart from the first dielectric.
Braunisch et al., however, discloses, in Fig. 6 and in paragraphs 48, 49 and 62, the silicon die (540) is laterally spaced apart from the first dielectric (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Yang et al. in view of Liu et al. in view of Pyo et al. with the disclosure of Braunisch et al. to have made the silicon die is laterally spaced apart from the first dielectric in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch et al.).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2018/0102311) in view of Yang et al. (U.S. Pub. 2010/0081236) in view of Pyo et al. (U.S. Pub. 2018/0175001).
Claim 18: Shih discloses a system, in annotated Fig. 14 below and in paragraphs 27, 39, 41, 49, 56, 59 and 60, comprising:
a package substrate (10), the package substrate (10) comprising:
a backside conductor (uppermost layer of 714);
an embedded multi-die interconnect bridge (101) over the backside conductor (uppermost layer of 714), the embedded multi-die interconnect bridge (101) having a first contact pad and a second contact pad thereon;
a first via, a second via and a third via (upper portion of 510) in a first level above the embedded multi-die interconnect bridge (101), the first via coupled to the first contact pad, the second via coupled to the second contact pad, and the third via (upper portion of 510) above and coupled to a fourth via (lower portion of 510) below the first level, the fourth via (lower portion of 510) laterally spaced apart from the embedded multi-die interconnect bridge (101);
a first conductive trace, a second conductive trace and a third conductive trace in a second level, the second level above the first level, the first conductive trace coupled to the first via, the second conductive trace coupled to the second via, and the third conductive trace coupled to the third via (upper portion of 510); and
a fifth via, a sixth via and a seventh via in a third level, the third level above the second level, the fifth via coupled to the first conductive trace, the sixth via coupled to the second conductive trace, and the seventh via coupled to the third conductive trace;
a first die (11) over the package substrate (10), the first die (11) over the embedded multi-die interconnect bridge (101) and over the backside conductor (upper portion of 714), and the first die (11) coupled to the fifth via and to the sixth via and to the seventh via; and
a second die (12) over the package substrate (10) and coupled to the embedded multi-die interconnect bridge (101).
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Shih appears not to explicitly disclose a printed circuit board; and
the package substrate coupled to the printed circuit board.
Shih, however, discloses in paragraph 52, discloses solder balls 801 may have a ball pitch that is equal to the ball pad pitch on a printed circuit board.
Therefore, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to the printed circuit board since the solder balls are spaced to have the same spacing as pads on a printed circuit board.
Further, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to a printed circuit board in order to connect the package substrate to other chips.
Shih also appears not to explicitly disclose an adhesive layer vertically between the embedded multi-die interconnect bridge and the backside conductor, the adhesive layer in contact with the embedded multi-die interconnect bridge.
Yang et al., however, discloses, in Fig. 16 and in paragraphs 92 and 95, an adhesive layer (31) vertically between the embedded multi-die interconnect bridge (10’) and the backside conductor (23), the adhesive layer in contact with the embedded multi-die interconnect bridge.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Yang et al. to have made an adhesive layer vertically between the embedded multi-die interconnect bridge and the backside conductor, the adhesive layer in contact with the embedded multi-die interconnect bridge in order to better secure the interconnect bridge to the underlying layer.
Shih also appears not to explicitly disclose wherein the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the embedded multi-die interconnect bridge.
Pyo et al., however, in Fig. 5 and in paragraph 46, discloses the backside conductor (140 below 200) is to receive a power supply voltage signal to provide vertical power distribution through the multi-die interconnect bridge (220).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Pyo et al. that is in the same field of endeavor with Shim et al., before the effective filing date of the claimed invention in order to substitute the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the embedded multi-die interconnect bridge as disclosed by Pyo et al. for power distribution disclosed by Shim et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the backside conductor is to receive a power supply voltage signal to provide vertical power distribution through the embedded multi-die interconnect bridge disclosed by Pyo et al. for the power distribution disclosed by Shim et al. would have yielded predictable results, namely providing a suitable power supply to the first die and the second die. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 19: Shih in view of Yang et al. in view of Pyo et al. discloses the system of claim 18, and Shih further discloses, in paragraph 60, wherein the second die (12) is coupled to the first die (11) by the embedded multi-die interconnect bridge (101).
Claim 20: Shih in view of Yang et al. in view of Pyo et al. discloses the system of claim 18, and Shih further discloses, in Fig. 14, wherein the backside conductor (uppermost layer of 714) comprises multiple regions that are electrically isolated from one another.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 and 8-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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