DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 31, 2025 has been entered. Claims 1-20 are under consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 9, 10, 12, 13, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 10,867,982 B1, herein “Yu”) in view of Zhang et al. (US 2022/0199600 A1, herein “Zhang”).
Regarding claims 1 and 2, Yu discloses a package structure (Fig. 23), comprising:
a bridge component (hybrid redistribution structure 104) having a first surface and a second surface opposite to the first surface;
an electro-optic conversion unit integrated in the photonic die (112) configured to convert optical signals to electrical signals or convert the electrical signals to the optical signals (Col. 4, lines 12-26);
a photonic processing unit (photonic dies 112) disposed over the first surface of the bridge component; and
an electrical device (electronic die 106) disposed over the first surface of the bridge component (hybrid redistribution structure 104),
wherein the bridge component is configured to optically coupled with the photonic processing unit and electrically connect with the electrical device (Col. 11, line 34 to Col. 12, line 2).
However Yu does not explicitly teach the electro-optic conversion unit embedded in the bridge component. Yu also does not explicitly teach the photonic processing unit is configured to receive a first optical signal from the bridge component and output a second optical signal to the bridge component in response to the first optical signal.
Zhang teaches an optical multichip package with multiple system-on-chip dies as shown in Fig. 2. The multichip package (MCP) shown in Fig. 2 incorporates the system-on-chip (SOC Core 208) system-on-chip I/O modules (SOC 202), and relaying on various forms of electrical interface (210) routing that may employs package routing, silicon bridge, interposer routing, or embedded multi die interconnect bridge (EMIB, Para [0026], [0029]). SOC I/O (202) electrically coupled with a separate PIC (206). The SOC (202 or 102) may contain I/O functionality that is required for proper functional integrated and communication with a PIC (206) using electrical signals that have been converted from optical signals received by the PIC (206) (Para [0027],[0028]). This conversion functionality is bi-directional in that optical signals can be converted to electrical signals. Therefore, the examiner considers the SOC 202 is a bridge component that an electro-optic conversion unit is embedded therein.
Zhang further teaches the SOC 202 (bridge) may contain I/O functionality in the form of I/O tile, that is required for proper functional integration and communication with a PIC 206 using electrical signals that have been converted from optical signals received by the PIC 206 (Para [0028]). Thus, the examiner considers Zhang’s bridge is capable of receiving the first optical signal from the bridge component via the I/O tile (input) and output via the I/O tile (output) a second optical signal to the bridge component (PIC 206) in response to the first optical signal. For this reason, the examiner considers the SOC 202 in Zhang’s invention is capable of performing the amended limitation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bridge component of Yu’s invention with the bridge component (SOC 202) of Zhang for the purpose of fully integrate with legacy components and architectures (Para [0027]). A motivation for integrating the multichip package with legacy components and architecture is to expand on existing infrastructures while upscaling bandwidth and density (Para [0027]).
Claim 8. Yu/Zhang teach the invention of claim 2, Zhang further teaches the bridge component (SOC 202) forming an overhang structure protruding over the wiring strung (210), and the package structure further comprises an optical fiber (214) optically coupled with the overhang structure of the bridge component and communicating with the photonic processing unit (SOC 202). See Zhang Fig. 2.
Yu/Zhang do not explicitly teach the optical fiber is non-overlapping with the photonic processing unit in a vertical direction.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the optical fiber provided by Yu/Zhang sends input and output signal into the multichip package. The benefits of this modification include easy access to the various chip modules.
Claim 9. Yu/Zhang teach the invention of claim 8, and Yu/Zhang teaches an optical fiber is coupled to PIC (206). The PIC (206) is configured for receiving the processed first optical signal and converting the processed first optical signal to an electrical signal (Yu: Col. 4, lines 12-26).
Yu/Zhang do not teach the second waveguide for transmitting the second optical signal from the photonic processing unit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of optical fibers to increase the input output capacity of the multichip package, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Regarding claim 10, Yu/Zhang teach the invention of claim 9, Zhang further teaches the bridge component (SOC 202) forming an overhang structure protruding over the wiring strung (210), and the package structure further comprises an optical fiber (214) optically coupled with the overhang structure of the bridge component and communicating with the photonic processing unit (SOC 202). See Zhang Fig. 2.
Regarding claims 12-13, Yu discloses a package structure comprising:
a signal transmission component (hybrid redistribution structure 104) comprising a plurality of optical I/O units (1354, 136) and a plurality of electrical I/O units (conductive connectors 258); and
an electro-optic conversion unit (photonic dies112) configured to convert optical signals to electrical signals or convert the electrical signals to the optical signals (Col. 4, lines 12-26),
wherein the signal transmission component comprises a first transmission path (waveguide 114) configured to transmit the optical signals from the optical I/O units (134, 136), and a second transmission path configured to transmit the electrical signals from or to the electrical I/O units, and wherein the electro-optic conversion unit connects with the first transmission path or the second transmission path or both (Col. 4, lines 12-26 and Fig. 23).
However, Yu does not teach an electro-optic conversion unit embedded in the signal transmission component. Yu also does not teach a photonic processing unit disposed over the signal transmission component and configured to receive a first optical signal of the optical signals from the signal transmission component and output a second optical signal of the optical signals to the signal transmission component in response to the first optical signal.
Zhang teaches an optical multichip package with multiple system-on-chip dies as shown in Fig. 2. The multichip package (MCP) shown in Fig. 2 incorporates the system-on-chip (SOC Core 208) system-on-chip I/O modules (SOC 202), and relaying on various forms of electrical interface (210) routing that may employs package routing, silicon bridge, interposer routing, or embedded multi die interconnect bridge (EMIB, Para [0026], [0029]). SOC I/O (202) electrically coupled with a separate PIC (206). The SOC (202 or 102) may contain I/O functionality that is required for proper functional integrated and communication with a PIC (206) using electrical signals that have been converted from optical signals received by the PIC (206) (Para [0027],[0028]). This conversion functionality is bi-directional in that optical signals can be converted to electrical signals. Therefore, the examiner considers the SOC 202 is a bridge component that an electro-optic conversion unit is embedded therein.
Zhang further teaches the SOC 202 (bridge) may contain I/O functionality in the form of I/O tile, that is required for proper functional integration and communication with a PIC 206 using electrical signals that have been converted from optical signals received by the PIC 206 (Para [0028]). Thus, the examiner considers Zhang’s bridge is capable of receiving the first optical signal from the bridge component via the I/O tile (input) and output via the I/O tile (output) a second optical signal to the bridge component (PIC 206) in response to the first optical signal. For this reason, the examiner considers the SOC 202 in Zhang’s invention is capable of performing the amended limitation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bridge component of Yu’s invention with the bridge component (SOC 202) of Zhang for the purpose of fully integrate with legacy components and architectures (Para [0027]). A motivation for integrating the multichip package with legacy components and architecture is to expand on existing infrastructures while upscaling bandwidth and density (Para [0027]).
Regarding claim 18, Yu discloses a package structure, comprising:
a bridge component (hybrid redistribution structure 104) having a first surface and a second surface opposite to the first surface, and a lateral surface extending between the first surface and second surface;
an electro-optic conversion unit integrated in the photonic die (112) configured to convert optical signals to electrical signals or convert the electrical signals to the optical signals (Col. 4, lines 12-26);
an electro-optic conversion unit integrated in the photonic die (112) configured to convert optical signals to electrical signals or convert the electrical signals to the optical signals (Col. 4, lines 12-26);
a photonic processing unit (photonic dies 112) disposed over the first surface of the bridge component.
However Yu does not explicitly teach the electro-optic conversion unit embedded in the bridge component and Yu does not teach an optical component optically connecting with the lateral surface of the bridge component, wherein the optical component communicates with the photonic processing unit through the bridge component.
Zhang teaches an optical multichip package with multiple system-on-chip dies as shown in Fig. 2. The multichip package (MCP) shown in Fig. 2 incorporates the system-on-chip (SOC Core 208) system-on-chip I/O modules (SOC 202), and relaying on various forms of electrical interface (210) routing that may employs package routing, silicon bridge, interposer routing, or embedded multi die interconnect bridge (EMIB, Para [0026], [0029]). SOC I/O (202) electrically coupled with a separate PIC (206). The SOC (202 or 102) may contain I/O functionality that is required for proper functional integrated and communication with a PIC (206) using electrical signals that have been converted from optical signals received by the PIC (206) (Para [0027],[0028]). This conversion functionality is bi-directional in that optical signals can be converted to electrical signals. Therefore, the examiner considers the SOC 202 is a bridge component that an electro-optic conversion unit is embedded therein.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bridge component of Yu’s invention with the bridge component (SOC 202) of Zhang for the purpose of fully integrate with legacy components and architectures (Para [0027]). A motivation for integrating the multichip package with legacy components and architecture is to expand on existing infrastructures while upscaling bandwidth and density (Para [0027]).
Yu/Zhang teach an optical fiber is coupled to PIC (206).
Yu/Zhang do not teach the bridge component comprises a waveguide adjacent to the first surface of the bridge component, and wherein the optical fiber is aligned with the first surface of the bridge component and optically coupled with the waveguide.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because rearranging the connecting port for the optical fiber (214) to the bridge (202) does not alter the function of the fiber being the signal I/O and conversion unit for converting the electrical signals to the optical signals remains embedded in the bridge (202). The benefit of coupling the fiber to the PIC (206) allows for higher overhang clearance over the base which allows for proper alignment.
Regarding claim 19, Yu/Zhang teach the invention of claim 18, but Yu/Zhang do not teach the bridge component is greater than a width of the wiring structure SOC Core (208) and the width of the wiring structure is greater than a width of the carrier (204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dimensions of the adjacent structures (e.g., wiring structure, bridge, and PIC) to optimize clearance space for coupling of an optical fiber, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). One motivation for optimizing the width of the bridge, wiring structure, and the carrier to provide an overhang and clearance for the coupler to side couple with an optical fiber.
Regarding claim 20, Yu/Zhang teach the invention of claim 19 and Zhang further teaches the first surface of the bridge component is substantially coplanar with a surface of the electro-optic conversion unit. Zhang teaches the SOC (202) is arranged coplanar with the SOC core (208) and PIC (206), since the electro-optic conversion unit is embedded within the SOC (202), and the conversion unit is 3-dimensional, then at least two of the three dimensions would necessarily be coplanar with the bridge (Para [0026]-[0029]).
Claim 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang as applied to claim 2 above, and further in view of Kubo et al. (US 2020/0174205 A1, herein “Kubo”).
Regarding claim 3, Yu/Zhang teach the invention of claim 2, but Yu/Zhang do not teach a modulator driver embedded in the wiring structure and configured to modulate the electrical signals to or from the electro-optic conversion unit.
Kubo teaches a photonic IC (105) has an optical circuit (106) formed by an optical waveguide. The optical circuit (106) carry out optical to electric conversion and electric to optical conversion are connected to the interconnects (15). The interconnects (16) are electrically connected via bonding wires (17) to an RF electrode (modulator driver) configured to apply a high-speed drive signal to the modulator. A DC electrode that applies a DC bias to the modulator, and an output electrode that outputs a photocurrent from a photodiode (Para [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design the wiring structure in Yu/Zhang’s invention to integrate the photonic IC circuit with interconnects and high speed drive signal to the modulator of Kubo’s invention as all inventors, Kubo, Yu, and Zhang are within in the same field of endeavor. One motivated for designing the modulator driver into the wiring structure of Yu/Zhang is to miniaturize and integrate the modulator into the multichip package for a more compact and cost-efficient device.
Regarding claim 11, Yu/Zhang teach the invention of claim 1, but Yu/Zhang is silent to the package structure further comprising a heat sink disposed over the bridge component and defining a cavity to accommodate the photonic processing unit and the electrical device.
Kubo teaches an optical package comprising a lid (15) is preferred to be made of copper, aluminum, zinc or the like (Para [0064]), which are all excellent material for conducting thermal energy away from the package. The examiner notes, the “heat sink” as disclosed the Specification is referenced to the lid (20) in Fig. 6 of the disclosure. Therefore, the examiner considers Kubo’s lid is equivalent as the heat sink as recited in the claim.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Yu/Zhang with a housing having a thermal conductive heat sink lid. The modification would necessarily dispose the heat sink over the bridge component and define a cavity to accommodate the photonic processing unit and the electrical device in Yu/Zhang’s invention. One motivation would be provide heat management to the package structure to prevent overheating.
Claims 4-5, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang as applied to claim 2 above, and further in view of Elsherbini et al. (US 12,406,962 B2, herein “Elsherbini”).
Regarding claim 4, Yu/Zhang teach the invention of claim 2, Yu/Zhang further teach conductive vias and through silicon vias to interlink the stacked chip packages.
However, Yu/Zhang do not explicitly teach a conductive pillar penetrating through the wiring structure and configured to transmit a power signal from the carrier to the bridge component.
Elsherbini teaches in Figs. 1A and 1B through silicon vias (TSV 132) can penetrate deeply through active region (142) into portions of metallization stack (130) providing conductive pathway from die-to-package substrate (DTPS) interconnects. TSV (132) maybe electrically coupled to other components in capacitor-die (106) to power grid or a ground grid (Col. 14, lines 53-61). Moreover, Elsherbini teaches the deep through silicon vias are assisted through interlayer dielectric (ILD) comprising conductive vias (146, Col. 14, lines 17-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the conductive vias and through silicon vias of Yu/Zhang with the deep through silicon vias design of Elsherbini such that the deep through silicon vias (conductive pillar) penetrate through the wiring structure (metallization stack or active region) for transmitting a power signal from the carrier to the bridge component. One motivation for employing deep through silicon vias is for power delivery in multi-stack integrated circuits to improve power integrity, reduce power consumption, and enhance thermal management.
Regarding claim 5, Yu/Zhang teach the invention of claim 2 and Yu/Zhang further teach a plurality of connection elements such as solder balls, micro bumps, bumps and other coupling technology between SOCS and PIC modules (Zhang: Para [0061]) and provide insulative molding around bump features and copper pillars or TSVs (Zhang: Para [0055], Fig. 6).
However, Yu/Zhang do not teach the protective element has a curved lateral surface.
Elsherbini teaches in Fig. 12 the wiring structure ball grid array (BGA) is protected by underfill material (2266) disposed between the package substrate, and wherein the protective element (underfill 2266) has a curved lateral surface (see curved edge at reference numeral 2266).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the flip-chip packaging technique is known since Yu, Zhang, and Elsherbini are within the same field of endeavor. The curved lateral surface of the underfill as recited in the claim is the result of the underfill shrinkage after curing. One motivation for designing a curved lateral surface in the underfill to provide a wider support base.
PNG
media_image1.png
338
477
media_image1.png
Greyscale
Regarding Claim 13, Yu/Zhang teach the invention of claim 12 wherein Zhang further teaches a third transmission path configured to transmit the optical signals from or to an optical fiber disposed adjacent to a lateral surface of the signal transmission component (Zhang: optical connector 662 may be lens to lens or a waveguide to waveguide coupling, an optical fiber coupling 664 may be optically coupled with optical connector 662, Para [0045]);
However, Yu/Zhang do not teach a fourth transmission path configured to transmit a power signal through a bottom surface of the signal transmission component.
Elsherbini teaches in Figs. 1A and 1B through silicon vias (TSV 132) can penetrate deeply through active region (142) into portions of metallization stack (130) providing conductive pathway from die-to-package substrate (DTPS) interconnects. TSV (132) maybe electrically coupled to other components in capacitor-die (106) to power grid or a ground grid (Col. 14, lines 53-61). Moreover, Elsherbini teaches the deep through silicon vias are assisted through interlayer dielectric (ILD) comprising conductive vias (146, Col. 14, lines 17-52). Therefore, the examiner considers the ILD is the fourth transmission path configured to transmit a power signal through a bottom surface of the signal transmission component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the conductive vias and through silicon vias of Yu/Zhang with the deep through silicon vias design of Elsherbini such that the deep through silicon vias (conductive pillar) penetrate through the wiring structure (metallization stack or active region) for transmitting a power signal from the carrier to the bridge component. One motivation for employing deep through silicon vias is for power delivery in multi-stack integrated circuits to improve power integrity, reduce power consumption, and enhance thermal management.
Regarding claim 14, Yu/Zhang in view of Elsherbini teach the invention of claim 13, and Zhang further teaches the signal transmission component, wherein the signal transmission component (SOC 202) may be offset from PIC (206) to form an overhang structure exposed from the protective element (underfill).
Regarding claim 15, Yu/Zhang in view of Elsherbini teach the optical fiber contacts the overhang structure (Zhang: Fig. 2) and transmits the optical signals to the photonic component through the first transmission path (PIC 206).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang in view of Elsherbini (herein “Yu/Zhang/Elsherbini”) as applied to claim 5 above, and further in view of Muramatsu et al. (US 2011/0316170 A1, herein “Muramatsu”).
Yu/Zhang/Elsherbini teach the invention of claim 5, but Yu/Zhang/Elsherbini do not teach a blocking structure disposed between the wiring structure and the bridge component, wherein the blocking structure is configured to block the protective element from contacting a lateral surface of the wiring structure.
Muramatsu teaches flip-chip mounting technique wherein a resin referred to as an underfilled is filled between the semiconductor chip and the wiring substrate. A wiring substrate may include a dam (blocking structure) to block the underfill resin on the solder resist layer near a chip mounting region of the wiring substrate. The dam is configured to block the underfill from contacting other mounting pads (Para [0005]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu/Zhang/Elsherbini to include a dam disposed between the wiring structure and the bridge component to block the underfill (protective element) from contacting a lateral surface of the wiring structure. One motivation for providing a dam is to prevent the underfill resin from overflowing and spread on the wiring substrate over an area that is more than necessary and thereby contaminate other mounting pads.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang/Elsherbini as applied to claim 5 above, and further in view of Moens et al. (US 2022/0020848 A1, herein “Moens”) .
Yu/Zhang/Elsherbini teach the invention of claim 5, but Yu/Zhang/Elsherbini is silent to the wiring structure has a trench, and a portion of the protective element is filled into the trench.
Moens teaches in Fig. 5 stacked chip package wherein isolation trenches (515) are filled with dielectric material or molding compound to electrically isolate the components (Para [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Yu/Zhang/Elsherbini to include isolation trench between the wiring structure and the bridge. One motivation would to be prevent electrical interference or crosstalk between closely packed circuit components on and between stacked dies.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang as applied to claim 8 and 14, respectively, above, and further in view of Ravichandran et al. (US 2022/0206221 A1, herein “Ravichandran”).
Regarding claim 10, Yu/Zhang teach the invention of claim 8, but Yu/Zhang is silent the package structure further comprising an adhesive material encapsulating a portion of the overhang structure and a coupling end of the optical fiber.
Ravichandran teaches in Fig. 1B a package structure with side fiber coupling region in PIC (110) connecting to fiber (120) forming an overhang. The fiber is secured to the overhang structure with an adhesive material (150) encapsulating a portion of the overhang structure and a coupling end of the optical fiber (120).
PNG
media_image2.png
307
403
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Yu/Zhang with an adhesive material encapsulating a portion of the overhang structure and a coupling end of the optical fiber for mechanically securing the edge-coupling joint. A motivation for securing the optical fiber to the overhang structure is to provide mechanical support at the coupling joint to prevent decoupling.
Regarding claim 17, Yu/Zhang/Elsherbini teach the invention of claim 14, but Yu/Zhang/Elsherbini is silent the package structure further comprising an adhesive material encapsulating a portion of the overhang structure and a coupling end of the optical fiber.
Ravichandran teaches in Fig. 1B a package structure with side fiber coupling region in PIC (110) connecting to fiber (120) forming an overhang. The fiber is secured to the overhang structure with an adhesive material (150) encapsulating a portion of the overhang structure and a coupling end of the optical fiber (120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Yu/Zhang/Elsherbini with an adhesive material encapsulating a portion of the overhang structure and a coupling end of the optical fiber for mechanically securing the edge-coupling joint. A motivation for securing the optical fiber to the overhang structure is to provide mechanical support at the coupling joint to prevent decoupling.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Zhang in view of Elsherbini (herein “Yu/Zhang/Elsherbini”) as applied to claim 15 above, and further in view of Kubo.
Yu/Zhang/Elsherbini teach the invention of claim 15, and Zhang further teaches the electro-optic conversion unit is configured to receive the optical signals from the photonic component (PIC 206) disposed over a top surface of the signal transmission component (SOC 202) through the optical I/O units, convert the optical signals to the electrical signals.
However, Yu/Zhang/Elsherbini do not teach transmit the electrical signals to a modulator driver disposed over the bottom surface of the signal transmission component through the electrical I/O units.
Kubo teaches a photonic IC (105) has an optical circuit (106) formed by an optical waveguide. The optical circuit (106) carry out optical to electric conversion and electric to optical conversion are connected to the interconnects (15). The interconnects (16) are electrically connected via bonding wires (17) to an RF electrode (modulator driver) configured to apply a high-speed drive signal to the modulator. A DC electrode that applies a DC bias to the modulator, and an output electrode that outputs a photocurrent from a photodiode (Para [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design the wiring structure in Yu/Zhang/Elsherbini’s invention to integrate the photonic IC circuit with interconnects and high speed drive signal to the modulator of Kubo’s invention as all inventors, Kubo, Yu, Zhang, and Elsherbini are within in the same field of endeavor. One motivated for designing the modulator driver into the wiring structure of Yu/Zhang is to miniaturize and integrate the modulator into the multichip package for a more compact and cost-efficient device.
Response to Arguments
Applicant’s arguments with respect to claim 1-20 have been considered. They focus on the newly added claim limitations which have been addressed and accounted for in the rejections above. Therefore all arguments are considered rebutted by the above rejections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874