Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 9/18/2025.
Claims 1-20 are currently pending.
Claims 12-20 have been withdrawn.
Claims 1-11 have been examined.
Election/Restriction
Applicant’s election without traverse of Invention I including claims 1-11 in the reply filed on 9/18/2025 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/18/2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 3/31/2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Interpretation
Regarding claim 2, the claim uses the term “less” for the size ranges of the gate structure and the source/drain structure. For clarity these two ranges are interpreted to be sizes at the nanometer scale from “0 to 12 nm” and “0 to 14 nm” respectively.
Claim Objection
Claims 2 and 4 objected to because of the following informalities:
Claim 2, the Examiner understands the term “critical dimension” to be the size that is critical to main features of a semiconductor device including size. In semiconductor manufacturing critical dimension inter alia could mean the minimum size of the feature on the mask or the minimum size of the feature in the working device or the most important measurement in order to make a working device. For the purposes of examination the “critical dimension” will be taken to mean the most important measurement in order to make a working device.
Claim 4 includes “ wherein the second interlayer dielectric is the same as the first interlayer dielectric.” The language is unclear because it implies that the second interlayer dielectric and the first interlayer dielectric are the same interlayer dielectric when they appear to two different dielectrics that may be the same material. Specification, [0031]. For purposes of examination, the Examiner will use the following interpretation of the claim “wherein the material of the second interlayer dielectric is the same material as the first interlayer dielectric.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 1 is rejected because claim 1 includes the term "overlies" is unclear because the term overlay/overlies could mean either to lay or spread over or covering and could be either direct or indirect. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Fig. 2 arguable provides insight into how the term overlies should be considered. However, as the drawing are schematics it does not properly provide meets and bounds that are searchable for the Examiner. For purposes of examination, the Examiner will use the following interpretation of the claim "the gate contact at least partly overlies in cross sectional view the first source/drain contact in a layer above the source/drain contact" in order to match the Examiner’s understanding of the claim according to Fig. 2.
Claims 2-11 are rejected based on their dependence to claim 1.
Claim 5 and 6 are rejected because claims 5 and 6 recite the term “an/the ear”. The term “ear” is not is not a standard term in semiconductor manufacture and the plain meaning of the term does not provide a clear meaning. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Fig. 2 arguable provides a shape that is the definition of the ear. However the drawing being a schematic, it does not properly provide meets and bounds that are searchable for the Examiner to find “an ear”. For the purposes of examination, the Examiner will interpret the claim as “the dielectric cap incorporates a third dielectric material which has at least one protrusion that protrudes between vertical surfaces of the first source/drain contact and the gate contact.”
Claim 6 is further rejected because claim 6 recites the limitation "the ear" in line 1 of claim 6. There is insufficient antecedent basis for this limitation in the claim. Claim 6 is dependent on claim 1 which does not introduce the term “an ear”. Claim 6 should either be rewritten to say “an ear” or depend on claim 5 which introduces “an ear.
Claim 8 is further rejected because claim 8 recites the term “a nub”. The term “a nub” is not is not a standard term in semiconductor manufacture and the plain meaning of the term does not provide a clear meaning. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Fig. 49 arguable provides a shape that is the definition of the nub. However the drawing, it does not properly provide meets and bounds that are searchable for the Examiner to find “a nub”. For the purposes of examination, the Examiner will interpret the claim as “the gate contact comprises a downward protrusion from the middle of the gate contact that protrudes from an inside corner of the first portion and the second portion into the dielectric cap.”
Allowable Subject Matter
Claims 1-11 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising "the gate contact at least partly overlies in cross sectional view the first source/drain contact in a layer above the source/drain contact"
Claim 1, Su et al. US 20220344496 A1 (hereinafter Su) teaches:
A metal-oxide-semiconductor field effect transistor (MOSFET) (Su, Fig. 14B) comprising:
a semiconductor substrate that has a frontside and a backside; (Su, [0012], the device is made on a substrate 201 which would inherently have a frontside and backside.)
a metal gate at the frontside of the substrate; (Fig. 14B, gate electrode 350, which is shown in a -z orientation the bottom in this case will be considered the frontside of the device. Figs. 2A-2C show the frontside before the inversion of the device along the z axis as part of the method of making the device.)
a first source/drain structure at the frontside of the substrate, adjacent to the metal gate in a first direction; (Fig. 14B, S/D feature 260)
a first source/drain contact at the frontside of the first source/drain structure; (Fig. 14B, S/D contacts 275.)
a backside power rail at the backside of the substrate; (backside power rails 284)
a recessed via that connects the first source/drain contact through the substrate to the backside power rail, wherein the recessed via is adjacent to the first source/drain structure in a direction perpendicular to the first direction; (Fig. 14B, backside via 282 and silicide feature 280 )
a dielectric cap that covers a frontside of the first source/drain contact; and (S/D capping layer 356)
a gate contact that is disposed at a frontside of the dielectric cap; (gate vias 359)
However, Chiang does not teach "the gate contact at least partly overlies in cross sectional view the first source/drain contact in a layer above the source/drain contact".
Hook et al. US 20190280113 A1 (hereinafter Hook) may be considered closest prior art which teaches in Fig. 19, a back gate 2310 which in the cross sectional overlay partly overlies the drain 2314. However, Hook teaches such overlap gate and drains for vertical transport FET devices (Hook, [0031]) and does not teach such overlap for horizontal transport FETs nor any motivation for combining the references. Therefore Hook does not teach "the gate contact at least partly overlies in cross sectional view the first source/drain contact in a layer above the source/drain contact," as examined.
The second closest prior art is Hsiung et al. US 20250096043 A1 (hereinafter Hsiung) which teaches a FinFET (Hsiung, [0011]) which has a second contact structure 1500 (Hsiung, Fig. 16A) which is over the gate structure 1000 and over the epitaxial structure 900 (Hsiung, [0047], i.e. source/drain region which is different from the source/drain contact per se). However, this gate structure 1000 is not over source/drain contact (Hsiung, Fig. 16A, third contact structure 1600). Therefor Hsiung does not teach "the gate contact at least partly overlies in cross sectional view the first source/drain contact in a layer above the source/drain contact," as examined.
Regarding claims 5, 6, and 8, they are allowable for the same reasons as claim 1 but should be further amended to overcome the further rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Regarding claims 2 and 4, they are allowable for the same reasons as claim 1 but should address the a objections set forth in this Office action above.
Regarding claims 3, 7, and 9-11 they are allowable for the same reasons as claim 1 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812