Prosecution Insights
Last updated: May 29, 2026
Application No. 18/129,258

METAL INSULATOR METAL (MIM) CAPACITOR ARCHITECTURES

Non-Final OA §103
Filed
Mar 31, 2023
Priority
Jun 16, 2022 — provisional 63/352,904
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
87%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
806 granted / 929 resolved
+18.8% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
955
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung (US 10396147) in view of Kiyomura Takatoshi (JP 2012124254), hereafter Kiyomura. Regarding claim 1, Leobandung discloses a metal insulator metal (MIM) capacitor, comprising: a first electrode (90) [Fig. 13]; an insulator (92 or 96) over the first electrode, wherein the insulator (92 or 96) extends laterally beyond an edge of the first electrode [Fig. 13]; a second electrode (98) over the insulator [Fig. 13]. However, Leobandung does not disclose the insulator comprising: a first layer; and a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer. Kiyomura teaches an insulator (3) over the first electrode [Fig. 1], wherein the insulator comprises: a first layer (3a); and a second layer (3b) over the first layer, wherein the first layer (3a) has a leakage current that is less than a leakage current of the second layer, and wherein the second layer (3b) has a dielectric constant that is greater than a dielectric constant of the first layer [Figs. 5-6 and English Machine Translation, pages 4-5]. Regarding claim 2, Kiyomura discloses wherein the first layer (3a) is a Sr-rich strontium titanium oxide (STO) layer, and the second layer (3b) is a Ti-rich STO layer [Figs. 5-6 and English Machine Translation, pages 4-5]. Regarding claim 3, Kiyomura discloses wherein one of the first layer (3a) or the second layer is a Sr-rich strontium titanium oxide (STO) layer (Sr/Ti > 1.0), and the other of the first layer or the second layer (3b) is a stoichiometric STO layer (Sr/Ti ratio = 1:1) [Figs. 5-6 and English Machine Translation, pages 4-5]. Also, see Figure 9, wherein the layer (3b) is the first layer, and the layer (3a) is the second layer. Regarding claim 4, Kiyomura discloses wherein the first layer has a thickness between approximately 1 nm and approximately 10 nm, and the second layer has a thickness between approximately 5 nm and approximately 30 nm [Fig. 2, and page 2 of English Machine Translation]. The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Regarding claim 5, Kiyomura discloses wherein the first layer (3a) has a dielectric constant of approximately 120, and the second layer (3b) has a dielectric constant of greater than 150 [Fig. 6 and English Machine Translation, pages 1 and 4-5]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Leobandung by including an insulator comprising: a first layer and a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer as taught by Kiyomura because it helps to improve leakage characteristics can be further improved [See page 4 of English Machine Translation]. Regarding claim 6, Leobandung discloses an integrated circuit structure comprising: a first build-up layer (20) having a trench (22) therein [Fig. 3]; a metal insulator metal (MIM) capacitor (90/92/94/96/98) in the trench [Fig. 13], the MIM capacitor comprising: a first electrode (90) [Fig. 13]; an insulator (92 or 96) over the first electrode, wherein the insulator (92 or 96) extends laterally beyond an edge of the first electrode [Fig. 13]. a second electrode (98) over the insulator [Fig. 13]; and a second build-up layer (80) over the first build-up layer and over the MIM capacitor, wherein a portion of the second build-up layer is in the trench [Fig. 13]. However, Leobandung does not disclose the insulator comprising: a first layer; and a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer. Kiyomura teaches an insulator (3) over the first electrode [Fig. 1], wherein the insulator comprises titanium and oxygen (STO), wherein the insulator comprises: a first layer (3a); and a second layer (3b) over the first layer, the second layer (3b) has a dielectric constant that is greater than a dielectric constant of the first layer (3a) [Figs. 5-6 and English Machine Translation, pages 1 and 4-5]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Leobandung by including an insulator comprising: a first layer and a second layer over the first layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer as taught by Kiyomura because it helps to improve leakage characteristics can be further improved [See page 4 of English Machine Translation]. Regarding claim 7, Leobandung discloses wherein the MIM capacitor further comprises a second insulator (96) over the second electrode (94), wherein the second insulator comprises titanium and oxygen, and a third electrode (98) over the second insulator [Fig. 13 and col. 7, lines 30-40]. Regarding claim 8, Leobandung discloses wherein the first electrode (90) or the second electrode (94) comprises a metal selected from the group consisting of Ru, RuO2, Ir, IrO2, Mo, Re, Ti, W, and Mo [col. 6, lines 1-7 and 54-62]. Regarding claim 9, Leobandung discloses wherein the insulator is a hafnium free insulating layer [col. 6, lines 39-45 and col. 7, lines 30-37]. Regarding claim 10, Leobandung wherein the insulator has a TiO2 composition [col. 6, lines 39-45 and col. 7, lines 30-37]. Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung (US 10396147) in view of Kiyomura Takatoshi (JP 2012124254), hereafter Kiyomura, and further in view of Lajoie et al. (US 2021/0098373). Regarding claim 11, Leobandung, as stated in the rejection of claim 1, discloses a metal insulator metal (MIM) capacitor. However, Leobandung does not disclose the insulator comprising: a first layer; and a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer; and a computing device. Kiyomura teaches an insulator (3) over the first electrode [Fig. 1], wherein the insulator comprises titanium and oxygen (STO), wherein the insulator comprises: a first layer (3a); and a second layer (3b) over the first layer, the second layer (3b) has a dielectric constant that is greater than a dielectric constant of the first layer (3a) [Figs. 5-6 and English Machine Translation, pages 1 and 4-5]. Further, Lajoie teaches Lajoie teaches a computing device (800) having a capacitor coupled to a board [Fig. 8 and paragraphs 0103-0104]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Leobandung by including an insulator comprising: a first layer and a second layer over the first layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer as taught by Kiyomura because it helps to improve leakage characteristics can be further improved [See page 4 of English Machine Translation]; and to further modify Leobandung by including a MIM capacitor coupled to a board as taught by Lajoie because it helps to increase densities of functional units on the limited real estate of semiconductor chips [paragraph 0002]. Regarding claim 12, Lajoie teaches a memory coupled to the board [Fig. 8 and paragraph 0104]. Regarding claim 13, Lajoie teaches a communication chip (806) coupled to the board [Fig. 8 and paragraph 0106]. Regarding claim 14, Lajoie teaches a camera coupled to the board [Fig, 8 and paragraph 0104]. Regarding claim 15, Lajoie teaches wherein the component is a packaged integrated circuit die [Fig. 8 and paragraph 0107]. Regarding claim 16, Leobandung, as stated in the rejection of claim 6, discloses a metal insulator metal (MIM) capacitor. However, Leobandung does not disclose the insulator comprising: a first layer; and a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer, and a computing device. Kiyomura teaches an insulator (3) over the first electrode [Fig. 1], wherein the insulator comprises titanium and oxygen (STO), wherein the insulator comprises: a first layer (3a); and a second layer (3b) over the first layer, the second layer (3b) has a dielectric constant that is greater than a dielectric constant of the first layer (3a) [Figs. 5-6 and English Machine Translation, pages 1 and 4-5]. Further, Lajoie teaches Lajoie teaches a computing device (800) having a capacitor coupled to a board [Fig. 8 and paragraphs 0103-0104]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Leobandung by including an insulator comprising: a first layer and a second layer over the first layer, wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer as taught by Kiyomura because it helps to improve leakage characteristics can be further improved [See page 4 of English Machine Translation]; and to further modify Leobandung by including a MIM capacitor coupled to a board as taught by Lajoie because it helps to increase densities of functional units on the limited real estate of semiconductor chips [paragraph 0002]. Regarding claim 17, Lajoie teaches a memory coupled to the board [Fig. 8 and paragraph 0104]. Regarding claim 18, Lajoie teaches a communication chip (806) coupled to the board [Fig. 8 and paragraph 0106]. Regarding claim 19, Lajoie teaches a camera coupled to the board [Fig, 8 and paragraph 0104]. Regarding claim 20, Lajoie teaches wherein the component is a packaged integrated circuit die [Fig. 8 and paragraph 0107]. Response to Arguments Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Mar 31, 2023
Application Filed
Sep 18, 2023
Response after Non-Final Action
Aug 28, 2025
Non-Final Rejection mailed — §103
Nov 25, 2025
Response Filed
Feb 12, 2026
Final Rejection mailed — §103
Apr 07, 2026
Response after Non-Final Action
May 12, 2026
Request for Continued Examination
May 18, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.5%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allowance rate.

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