CTNF 18/129,315 CTNF 74962 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This office action is in response to application 18/129315 filed on 03/31/23. Summary of claims Claims 1-20 are pending. Claims 1-20 are rejected. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Case et al. (US Pub. 2022/0018896) . As to claim 1 the prior art teaches an apparatus, comprising: a model chiplet for semiconductor testing, the model chiplet having a test interface, a model logic feature and model test logic, the model logic feature to comprise a known good model (KGM) for a logic feature defined by a semiconductor specification, the model test logic to: receive a control signal from the test interface, the control signal to initiate testing of a device under test (DUT) (see fig 1 element 20) logic feature of a DUT chiplet (see fig 1 paragraph 0013-0016); send test information over an interconnect in response to the control signal, the test information designed to test the DUT logic feature of the DUT chiplet (see fig 1-3 paragraph 0015-0020); receive response information over the interconnect in response to the test information, the response information associated with the DUT logic feature of the DUT chiplet (see fig 1-3 paragraph 0020-0024); generate a measurement for the DUT logic feature based on the response information (see fig 1-3 paragraph 0036-0040); and send the measurement for the DUT logic feature to the test interface (see fig 2-4 paragraph 0040-0046). As to claim 2, 11 and 19 the prior art teaches wherein the logic feature is defined by a semiconductor specification, the semiconductor specification to comprise a universal chiplet interconnect express (UCle) specification (see fig 1 paragraph 0014-0018). As to claim 3, 15 and 20 the prior art teaches the model chiplet having logic for a physical layer, an adapter and a protocol layer for an interconnect, the adapter to receive flow control unit (FCU) level interface transfer (FLIT) aware die-to-die (D2D) interface (FDI) data from the protocol layer, and output raw D2D interface (RDI) data to the physical layer for transport over the interconnect to the DUT chiplet (see fig 2-4 paragraph 0027-0030). As to claim 4 and 16 the prior art teaches the model chiplet having an adapter, the adapter to include a compliance flow control unit (FCU) level interface transfer (FLIT) injector, the compliance FLIT injector to generate a set of test FLITs in a test pattern to test the DUT chiplet (see fig 1-2 paragraph 0023-0027). As to claim 5 and 17 the prior art teaches the model test logic to comprise a pattern generator, a loopback generator, a droop detector, a process monitor, an oscilliscope, or a ring oscillator (see fig 1-3 paragraph 0029-0032). As to claim 6 the prior art teaches the DUT chiplet having a test interface, the DUT logic feature and DUT test logic, the DUT logic feature to comprise an unknown model for the logic feature in accordance with a semiconductor specification, the DUT test logic to receive the test information over the interconnect, generate the response information associated with the DUT logic feature, and send the response information over the interconnect to the model chiplet (see fig 2-4 paragraph 0042-0046). As to claim 7 and 14 the prior art teaches the DUT chiplet having logic for a physical layer, an adapter and a protocol layer for an interconnect, the adapter to receive flow control unit (FCU) level interface transfer (FLIT) aware die-to-die (D2D) interface (FDI) data from the protocol layer, and output raw D2D interface (RDI) data to the physical layer for transport over the interconnect to the model chiplet (see fig 2-4 paragraph 0028-0032). As to claim 8 and 16 the prior art teaches the DUT chiplet having an adapter, the adapter to include a compliance flow control unit (FCU) level interface transfer (FLIT) injector, the compliance FLIT injector to generate a set of test FLITs in a test pattern to test the DUT chiplet (see fig 1-3 paragraph 0043-0047). As to claim 9 the prior art teaches the DUT chiplet having DUT test logic, the DUT test logic to comprise a compliance manager, a header manager, a pattern generator, a state manager, a protocol manager, or a graph manager (see fig 3-5 paragraph 0039-0043). As to claim 10 the prior art teaches a system, comprising: circuitry to manage semiconductor testing, the circuitry arranged to: send a control signal to a model chiplet to initiate semiconductor testing, the model chiplet to comprise a model logic feature that is a known good model (KGM) of a logic feature defined by a semiconductor specification (see fig 1 paragraph 0013-0016); receive a measurement from the model chiplet in response to the control signal to initiate semiconductor testing, the measurement associated with a device under testing (DUT) logic feature of a DUT chiplet, the DUT logic feature to comprise an unknown good model (UGM) of the logic feature defined by the semiconductor specification (see fig 1-3 paragraph 0017-0021); compare the measurement for the DUT logic feature to an evaluation criterion to form result information, the evaluation criterion defined by the semiconductor specification (see fig 1-3 paragraph 0020-0026); and determine whether the DUT logic feature meets the evaluation criterion of the semiconductor specification based on the result information (see fig 1-3 paragraph 0039-0043). As to claim 12 the prior art teaches comprising a set of test connections communicatively coupled to the test device and a test package, the test package to comprise the model chiplet, the DUT chiplet and an interconnect to transmit signals between the model chiplet and the DUT chiplet, the test package to comprise a standard test package or an advanced test package (see fig 2-4 paragraph 0032-0037). As to claim 13 the prior art teaches comprising a test package coupled to the test device via a test connection, the test package having the model chiplet, the DUT chiplet and an interconnect to transmit signals between the model chiplet and the DUT chiplet, the test package to comprise a standard test package or an advanced test package (see fig 2-4 paragraph 0049-0054). As to claim 14 the prior art teaches comprising the model chiplet, the a model chiplet for semiconductor testing, the model chiplet having a test interface, a model logic feature and model test logic, the model logic feature to comprise a known good model (KGM) for a logic feature defined by a semiconductor specification (see fig 3-6 paragraph 0047-0050). As to claim 18 the prior art teaches a method, comprising: sending a control signal to a model chiplet to initiate semiconductor testing, the model chiplet to comprise a model logic feature that is a known good model (KGM) of a logic feature defined by a semiconductor specification (see fig 1 paragraph 0013-0016); receiving a measurement from the model chiplet in response to the control signal to initiate semiconductor testing, the measurement associated with a device under testing (DUT) logic feature of a DUT chiplet, the DUT logic feature to comprise an unknown good model (UGM) of the logic feature defined by the semiconductor specification (see fig 1-3 paragraph 0017-0021); comparing the measurement for the DUT logic feature to an evaluation criterion to form result information, the evaluation criterion defined by the semiconductor specification (see fig 1-3 paragraph 0020-0026); and determining whether the DUT logic feature meets the evaluation criterion of the semiconductor specification based on the result information (see fig 1-3 paragraph 0039-0043). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /BINH C TAT/Primary Examiner, Art Unit 2851 Application/Control Number: 18/129,315 Page 2 Art Unit: 2851 Application/Control Number: 18/129,315 Page 3 Art Unit: 2851 Application/Control Number: 18/129,315 Page 4 Art Unit: 2851 Application/Control Number: 18/129,315 Page 5 Art Unit: 2851 Application/Control Number: 18/129,315 Page 6 Art Unit: 2851 Application/Control Number: 18/129,315 Page 8 Art Unit: 2851
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