DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The Examiner acknowledges that the amendments to claims 1 and 7 resolves the previous rejection of claims 1 and 7. Therefore, the previous rejection of claims 1-9 under 35 USC 112(b) have been withdrawn.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, claim 8 recites “the gate metal contact”. However, neither of earlier in claim 8 nor in claim 1 from which claim 8 depends is “a gate metal contact” recited. Instead, claim 1 recites “a gate contact”. Therefore, the gate metal contact lacks proper antecedent basis and it is unclear whether the gate metal contact is the same or different structure from the “a gate contact”. Appropriate correction should be made to resolve the antecedent basis issue. For purposes of compact prosecution the Examiner interprets the claim language to be that the “the gate metal contact” in claim 8 is the same structure as the “a gate contact” in claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Jeon et al. (US 2016/0336313) hereinafter “Jeon”.
Regarding claim 1, Fig. 2 of Zhang teaches a semiconductor device structure comprising an enhancement-mode GaN semiconductor power transistor (Paragraphs 0002 and 0003) comprising: an epitaxial layer structure (Paragraph 0066) comprising a semiconductor substrate (Item 10), a buffer layer (Item 11; Paragraph 019), a GaN semiconductor heterostructure comprising a GaN channel layer (Item 12; Paragraph 0023) and AlGaN barrier layer (Item 13; Paragraph 0023) providing a 2DEG active region (Item 0023); a p-GaN layer (Item 14) patterned to define a p-GaN gate region; a first passivation layer (Item 16); contact openings through the first passivation layer (Item 16); ohmic contact metal (Paragraph 0071) within said contact openings which is patterned to form a source contact (Item S) and a drain contact (Item D); a second passivation layer (Item 17); a gate contact opening through the first and second passivation layers (Items 16 and 17) to the p-GaN gate region (Item 14); gate metal (Combination of Items 15 and G) within the gate contact opening patterned to form a gate contact; one or more dielectric layers (Item 18; Paragraph 0086) extending over the epitaxial layer structure (Paragraph 0066), the first passivation layer (Item 16), the second passivation layer (Item 17), the source contact (Item S), the drain contact (Item D), and the gate contact (Combination of Items 15 and G); openings into the one or more dielectric layers for a stepped opening for a stepped gate field plate (Item 22); at least one layer of conductive metal filling each of said openings to form the stepped gate field plate (Item 22).
Zhang does not teach the one or more dielectric layers are substantially planar dielectric layers and the one or more dielectric layers comprise one or more etch stop layers.
Fig. 6 of Jeon teaches where one or more dielectric layers (Item 232) are substantially planar dielectric layers and comprise etch stop layers (Paragraph 0037 where the insulating layer is a plurality of films, where insulating layer acts as etch stop layers and where the bottoms of the stepped hole [Item 274] in the dielectric layer [Item 232] are planar).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more dielectric layers be substantially planar dielectric layers that are etch stop layers because this allows the dielectric layers to act as an etch stop film during the formation of the structure (Jeon Paragraph 0037).
Zhang does not teach openings in the one or more dielectric layers for conductive source and drain contact structures electrically contacting the source contact and the drain contact, respectively, at least one layer of conductive metal filling each of the openings to form the conductive source and drain contact structures.
Fig. 6 of Jeon teaches openings in the one or more dielectric layers (Item 232) for conductive source (Item 252) and drain (Item 258) contact structures electrically a source and a drain, respectively, at least one layer of conductive metal filling each of the openings to form the conductive source and drain contact structures (Paragraph 0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have openings in the one or more dielectric layers for conductive source and drain contact structures electrically contacting the source contact and the drain contact, respectively, at least one layer of conductive metal filling each of the openings to form the conductive source and drain contact structures because this allows the source and drain of the enhancement mode GaN semiconductor power transistor to be connected to conductive lines above the dielectric layer and other external structures (Jeon Paragraph 0045).
Examiner’s Note: The Examiner notes that “openings etched into said one or more dielectric layers” is a product by process limitation. As the claim is a product and forming the openings by etching is drawn to the method of forming the product the claim language only requires the presence of the openings in the one or more dielectric layers but not that they are formed bv etching.
Regarding claim 2, the combination of Zhang and Jeon teaches all of the elements of the claimed invention as stated above.
Zhang does not teach where the one or more dielectric layers comprise a plurality of substantially planar dielectric layers, and the stepped opening for the stepped gate field plate is defined by substantially planar portions of the plurality of substantially planar dielectric layers.
Fig. 6 of Jeon teaches the one or more dielectric layers (Item 232) comprise a plurality of substantially planar dielectric layers (Paragraph 0037), and the stepped opening for the stepped gate field plate is defined by substantially planar portions of the plurality of substantially planar dielectric layers (Paragraph 0037).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more dielectric layers comprise a plurality of substantially planar dielectric layers, and the stepped opening for the stepped gate field plate is defined by substantially planar portions of the plurality of substantially planar dielectric layers because the substantially planar dielectric layers act as etch stop layers during the formation of the respective portions of the structure (Jeon Paragraph 0037).
Regarding claim 3, Fig. 2 of Zhang further teaches where a thickness of the first and second passivation layers (Items 16 and 17) under the stepped gate field plate (Item 22), and a step size of each step of the stepped gate field plate (Item 22) are configured to shape an electric field under the stepped gate field plate between the gate contact and the drain contact (Paragraphs 0041 and 0042).
Regarding claim 7, the process limitation of “where the gate contact is formed by a lift-off metal process” found in product claim 7 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 7 does not require the gate metal contact to be formed by a lift-off metal process, but simply that a gate metal contact is present in the structure. Zhang further teaches a gate metal contact (Combination of Items G and 15).
Regarding claim 8, the process limitation of “where the gate contact is formed by deposition and etching of the gate metal” found in product claim 8 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 8 does not require the gate metal contact to be formed by a deposition and etching process, but simply that a gate metal contact is present in the structure. Zhang further teaches a gate metal contact (Combination of Items G and 15).
Regarding claim 9, the combination of Zhang and Jeon teach all of the elements of the claimed invention as stated above.
Zhang does not teach where the one or more dielectric layers comprises a plurality of substantially planar dielectric layers comprising the one or more etch stop layers, the stepped openings for the stepped gate field plate being defined by the plurality of substantially planar dielectric layers.
Fig. 6 of Jeon teaches where one or more dielectric layers (Item 232) are substantially planar dielectric layers and comprise etch stop layers (Paragraph 0037 where the insulating layer is a plurality of films, where insulating layer acts as etch stop layers and where the bottoms of the stepped hole [Item 274] in the dielectric layer [Item 232] are planar) where the stepped openings are defined by the plurality of substantially planar dielectric layers (Paragraph 0037).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more dielectric layers comprise a plurality of substantially planar dielectric layers comprising the one or more etch stop layers, the stepped openings for the stepped gate field plate being defined by the plurality of substantially planar dielectric layers because this allows the dielectric layers to act as an etch stop film during the formation of the structure (Jeon Paragraph 0037).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Jeon et al. (US 2016/0336313) hereinafter “Jeon”. and in further view of Padmanabhan et al. (US 2014/0264369) hereinafter “Padmanabhan”.
Regarding claim 4, the combination of Zhang and Jeon teaches all of the elements of the claimed invention as stated above except where the least one layer of conductive metal comprises a single metal layer.
Fig. 29 of Padmanabhan teaches where a conductive metal layer that forms a source contact (Item 36), a drain contact (Item 37) and a field plate (Item 38) is a single metal layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the least one layer of conductive metal comprises a single metal layer because using a single layer for the source, drain and field plate allows for the structures to be formed in a single step (Padmanabhan Paragraph 0027).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Jeon et al. (US 2016/0336313) hereinafter “Jeon”. and in further view of Ito (US 2024/0030336) hereinafter “Ito”.
Regarding claim 5, the combination of Zhang and Jeon teaches all of the elements of the claimed invention as stated above except where the at least one layer of conductive metal comprises a plurality of metal layers.
Ito teaches where a source electrode (Item 28A), a drain electrode (Item 30) and a field plate (Item 28B) include one or more metal layers (Paragraph 0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the at least one layer of conductive metal comprise a plurality of metal layers because a contact using more than one metal layers is known to effectively form a source, drain and field plate (Ito Paragraph 0041).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Jeon et al. (US 2016/0336313) hereinafter “Jeon”. and in further view of Bothe et al. (US 2023/0261054) hereinafter “Bothe”.
Regarding claim 6, the combination of Zhang and Jeon teaches all of the elements of the claimed invention as stated above except an opening in the one or more dielectric layers for an interconnect trace connecting the source contact and the stepped gate field plate, the opening for the interconnect trace being filled with conductive metal.
Fig. 1 of Bothe teaches where dielectric layer (Item 34) includes an openings for an interconnect trace (Item 29) connecting a source contact (Item 26) and a stepped field plate (Item 28), the opening for the interconnect trace being filled with conductive metal.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an opening in the one or more dielectric layers for an interconnect trace connecting the source contact and the stepped gate field plate, the opening for the interconnect trace being filled with conductive metal because the opening would allow the source contact to be electrically connected to the field plate (Bothe Paragraph 0072).
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS, filed 07/07/2026, with respect to the rejection(s) of claim(s) 1 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jeon.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/
Primary Examiner, Art Unit 2891
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