Prosecution Insights
Last updated: July 17, 2026
Application No. 18/129,457

GaN SEMICONDUCTOR POWER TRANSISTORS WITH STEPPED METAL FIELD PLATES AND METHODS OF FABRICATION

Non-Final OA §102§103§112
Filed
Mar 31, 2023
Examiner
ASHBAHIAN, ERIC K
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Canada Inc.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
327 granted / 486 resolved
-0.7% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
35 currently pending
Career history
536
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
82.3%
+42.3% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
4.9%
-35.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 486 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (Claims 1-9) in the reply filed on 09/09/2025 is acknowledged. Claims 10-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/09/2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, claim 1 recites “one or more dielectric layers extending overall”. However, it is unclear what the metes and bounds of “overall” are. Therefore it is unclear what structure or structures are required by the claim for the one or more dielectric layers to extend over. Appropriate correction is required to clarify the language. For purposes of compact prosecution the Examiner will interpret the language as requiring the one or more dielectric layers extending over the expitaxial layer structure, p-GAN gate region, ohmic contacts and first and second passivation layers. Claims 2-9 are also rejected under 35 USC 112(b) as they depend from and include all of the limitations of rejected claim 1. Regarding claim 7, claim 7 recites “the gate metal contact”. However, neither of earlier in claim 7 nor in claim 1 from which claim 7 depends is “a gate metal contact” recited. Instead, claim 1 recites “a gate contact”. Therefore, the gate metal contact lacks proper antecedent basis and it is unclear whether the gate metal contact is the same or a different structure from the “a gate contact”. For purposes of compact prosecution the Examiner interprets the claim language to be that the “the gate metal contact” in claim 7 is the same structure as of the “a gate contact” in claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Zhang et al. (US 2021/0384303) hereinafter “Zhang”. Regarding claim 1, Fig. 2 of Zhang teaches a semiconductor device structure comprising an enhancement-mode GaN semiconductor power transistor (Paragraphs 0002 and 0003) comprising: an epitaxial layer structure (Paragraph 0066) comprising a semiconductor substrate (Item 10), a buffer layer (Item 11; Paragraph 019), a GaN semiconductor heterostructure comprising a GaN channel layer (Item 12; Paragraph 0023) and AlGaN barrier layer (Item 13; Paragraph 0023) providing a 2DEG active region (Item 0023); a p-GaN layer (Item 14) patterned to define a p-GaN gate region; a first passivation layer (Item 16); contact openings through the first passivation layer (Item 16) for source contacts (Item S) and drain contacts (Item S); ohmic contact metal (Paragraph 0071) within said contact openings which is patterned to form source contacts (Item S) and drain contacts (Item D); a second passivation layer (Item 17); a gate contact opening through the first and second passivation layers (Items 16 and 17) to the p-GaN gate region (Item 14); gate metal (Combination of Items 15 and G) within the gate contact opening patterned to form a gate contact; one or more dielectric layers (Item 18) extending overall; openings in or more dielectric layers for a source contact (Item S), a drain contact (Item D) and a stepped gate field plate (Item 22); at least one layer of conductive metal filling each of said openings (See Examiner’s Note 2 below) and forming the source contact (Item S), the drain contact (Item D) and the stepped gate field plate (Item 22). Examiner’s Note: The Examiner notes that “openings etched into said one or more dielectric layers” is a product by process limitation. As the claim is a product and forming the openings by etching is drawn to the method of forming the product the claim language only requires the presence of the openings in the one or more dielectric layers but not that they are formed bv etching. Examiner’s Note 2: The Examiner notes that the language of the claim does not require that the at least one layer of conductive metal filling each of the openings in the at least one dielectric layer is different from the ohmic contact metal within the contact openings. Therefore, portions of Item S in the at least one dielectric layer and the ohmic contact metal within the contact openings through the first passivation layer can be the same ohmic metal layer. Regarding claim 3, Fig. 2 of Zhang further teaches where a thickness of the first and second passivation layers (Items 16 and 17) under the stepped gate field plate (Item 22), and a step size of each step of the stepped gate field plate (Item 22) are configured to shape an electric field under the stepped gate field plate between the gate contact and the drain contact (Paragraphs 0041 and 0042). Regarding claim 7, the process limitation of “where the gate metal contact is formed by a lift-off metal process” found in product claim 7 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 7 does not require the gate metal contact to be formed by a lift-off metal process, but simply that a gate metal contact is present in the structure. Zhang further teaches a gate metal contact (Combination of Items G and 15). Regarding claim 8, the process limitation of “where the gate metal contact is formed by deposition and etching of the gate metal” found in product claim 8 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 8 does not require the gate metal contact to be formed by a deposition and etching process, but simply that a gate metal contact is present in the structure. Zhang further teaches a gate metal contact (Combination of Items G and 15). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Teplik et al. (US 2014/0061659) hereinafter “Teplik”. Regarding claim 2, Zhang teaches all of the elements of the claimed invention as stated above except where the one or more dielectric layers comprise one or more etch stop layers. Teplik teaches a device having a multi-region field plate which has a plurality of distances between the field plate and the channel layer, where a dielectric layer in which the field plate is present comprises one or more intermediate dielectric etch stop layers (Paragraph 0011). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more dielectric layers comprise one or more etch stop layers because the one or more etch stop layers can be used during a process to manufacture the field plate such that the field plate is a multi-region field plate (Teplik Paragraph 0011). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Padmanabhan et al. (US 2014/0264369) hereinafter “Padmanabhan”. Regarding claim 4, Zhang teaches all of the elements of the claimed invention as stated above except where the least one layer of conductive metal comprises a single metal layer. Fig. 29 of Padmanabhan teaches where a conductive metal layer that forms a source contact (Item 36), a drain contact (Item 37) and a field plate (Item 38) is a single metal layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the least one layer of conductive metal comprises a single metal layer because using a single layer for the source, drain and field plate allows for the structures to be formed in a single step (Padmanabhan Paragraph 0027). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Ito (US 2024/0030336) hereinafter “Ito”. Regarding claim 5, Zhang teaches all of the elements of the claimed invention as stated above except where the at least one layer of conductive metal comprises a plurality of metal layers. Ito teaches where a source electrode (Item 28A), a drain electrode (Item 30) and a field plate (Item 28B) include one or more metal layers (Paragraph 0041). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the at least one layer of conductive metal comprise a plurality of metal layers because a contact using more than one metal layers is known to effectively form a source, drain and field plate (Ito Paragraph 0041). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Bothe et al. (US 2023/0261054) hereinafter “Bothe”. Regarding claim 6, Zhang teaches all of the elements of the claimed invention as stated above except an opening in the one or more dielectric layers for an interconnect trace connecting the source contact and the stepped gate field plate, the opening for the interconnect trace being filled with conductive metal. Fig. 1 of Bothe teaches where dielectric layer (Item 34) includes an openings for an interconnect trace (Item 29) connecting a source contact (Item 26) and a stepped field plate (Item 28), the opening for the interconnect trace being filled with conductive metal. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an opening in the one or more dielectric layers for an interconnect trace connecting the source contact and the stepped gate field plate, the opening for the interconnect trace being filled with conductive metal because the opening would allow the source contact to be electrically connected to the field plate (Bothe Paragraph 0072). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0384303) hereinafter “Zhang” in view of Grote et al. (US 2022/0376060) hereinafter “Grote” and in further view of Teplik et al. (US 2014/0061659) hereinafter “Teplik” and Ito (US 2024/0030336) hereinafter “Ito”. Regarding claim 9, Zhang teaches all of the elements of the claimed invention as stated above except where the one or more dielectric layers comprises a plurality of dielectric layers which are etched to form the stepped openings; and the at least one layer of conductive metal comprises a plurality of metal layers filling the stepped openings to form a stepped source contact, a stepped drain contact and stepped gate field plate. Zhang further teaches where the source contact (Item S), the drain contact (Item D) and the field plate (Item 22) are stepped structures. Zhang does not teach where the openings in the at least one or more dielectric layers are stepped openings. Fig. 2 of Grote teaches where openings in at least one or more dielectric layers are stepped openings such that stepped source and drain contacts are present. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the openings in the at least one or more dielectric layers be stepped openings because this allows the formation of stepped source and drain contacts to be present in the a final device structure (Grote Paragraph 0026). Teplik teaches a device having a multi-region field plate which has a plurality of distances between the field plate and the channel layer, where a dielectric layer in which the field plate is present comprises one or more intermediate dielectric etch stop layers (Paragraph 0011). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more dielectric layers comprises a plurality of dielectric layers which are etched to form the stepped openings because the one or more etch stop layers can be used during a process to manufacture the field plate such that the field plate is a multi-region field plate (Teplik Paragraph 0011). Ito teaches where a source electrode (Item 28A), a drain electrode (Item 30) and a field plate (Item 28B) include one or more metal layers (Paragraph 0041). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the at least one layer of conductive metal comprises a plurality of metal layers filling the stepped openings to form a stepped source contact, a stepped drain contact and stepped gate field plate because a contact using more than one metal layers is known to effectively form a source, drain and field plate (Ito Paragraph 0041). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC K ASHBAHIAN/ Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Mar 31, 2023
Application Filed
Apr 20, 2026
Non-Final Rejection mailed — §102, §103, §112
Jul 07, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
73%
With Interview (+5.6%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 486 resolved cases by this examiner. Grant probability derived from career allowance rate.

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