DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ouellette et al (US Publication No. 2022/0093597) in view of Cheng (US Publication No. 2021/0384313) and Park et al (US Publication No. 2021/0028291).
Regarding claim 1, Ouellette discloses an integrated circuit structure Fig 2A-2E, comprising: a first vertical arrangement of horizontal nanowires Fig 2E, 210; a second vertical arrangement of horizontal nanowires Fig 2E, 208; a PMOS gate stack over the first vertical arrangement of horizontal nanowires Fig 2E, the PMOS gate stack having a layer molybdenum structure Fig 2E, 224 ¶0064 on a first gate dielectric Fig 2E, 211; and an NMOS gate stack over the second vertical arrangement of horizontal nanowires Fig 2E, the NMOS gate stack having the multi-layer molybdenum structure Fig 2E, 214 ¶0044 on a second gate dielectric Fig 2E, 209; a conductive fill on the molybdenum structure Fig 2E. Ouellette discloses all the limitations but silent on a multi-layer molybdenum structure for the PMOS gate stack. Whereas Cheng discloses a PMOS gate stack having a multi-layer molybdenum structure Fig 19A-19F ¶0026, 0081-0082. While Park discloses a conductive fill on the multi-layer molybdenum structure, the conductive fill separate and distinct from the multi-layer molybdenum structure ¶0087, 0092 Fig 15.
Ouellette, Cheng and Park are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ouellette because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the material used for the PMOS device and incorporate the teachings of Cheng/Park
since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 2, Ouellette discloses wherein the multi-layer molybdenum structure comprises a layer comprising molybdenum on a layer comprising molybdenum and nitrogen ¶0044 and 0064.
Regarding claim 3, Ouellette discloses wherein the layer comprising molybdenum is thicker than the layer comprising molybdenum and nitrogen Fig 2E.
Regarding claim 4, Cheng discloses wherein the second gate dielectric comprises an N-type dipole material layer comprising lanthanum and oxygen ¶0066.
Regarding claim 5, Cheng discloses wherein the second gate dielectric comprises an N-type dipole material layer comprising magnesium and oxygen¶0066.
Regarding claim 6, Ouellette discloses an integrated circuit structure Fig 2A-2E, comprising: a first vertical arrangement of horizontal nanowires Fig 2E, 210; a second vertical arrangement of horizontal nanowires Fig 2E, 208; a PMOS gate stack over the first vertical arrangement of horizontal nanowires Fig 2E, the PMOS gate stack having a layer molybdenum structure Fig 2E, 224 ¶0064 on a first gate dielectric Fig 2E, and an NMOS gate stack over the second vertical arrangement of horizontal nanowires Fig 2E, the NMOS gate stack having an N-type conductive layer Fig 2E, 214 ¶0044 on a second gate dielectric Fig 2E, 209. Ouellette discloses all the limitations but silent on a multi-layer molybdenum structure for the PMOS gate stack. Whereas Cheng discloses a PMOS gate stack having a multi-layer molybdenum structure Fig 19A-19F ¶0026, 0081-0082. While Park discloses a conductive fill on the multi-layer molybdenum structure, the conductive fill separate and distinct from the multi-layer molybdenum structure ¶0087, 0092 Fig 15. Ouellette, Cheng and Park are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ouellette because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the material used for the PMOS device and incorporate the teachings of Cheng/Park since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 7, Ouellette discloses wherein the multi-layer molybdenum structure comprises a layer comprising molybdenum on a layer comprising molybdenum and nitrogen ¶0044 and 0064.
Regarding claim 8, Ouellette discloses wherein the layer comprising molybdenum is thicker than the layer comprising molybdenum and nitrogen Fig 2E.
Regarding claim 9, Ouellette discloses wherein the first gate dielectric comprises a high-k dielectric laye¶0164 Claim 9.
Regarding claim 10, Ouellette discloses wherein the second gate dielectric comprises the high-k dielectric layer on a dipole material layer ¶0164 Claim 9.
Regarding claim 11, Ouellette discloses a computing device, comprising: a board ¶0171; and a component coupled to the board Fig 9, the component including an integrated circuit structure Fig 2A-2E, comprising: a first vertical arrangement of horizontal nanowires Fig 2E, 210; a second vertical arrangement of horizontal nanowires Fig 2E, 208; a PMOS gate stack over the first vertical arrangement of horizontal nanowires Fig 2E, the PMOS gate stack having a layer molybdenum structure Fig 2E, 224 ¶0064 on a first gate dielectric Fig 2E, 211; and an NMOS gate stack over the second vertical arrangement of horizontal nanowires Fig 2E, the NMOS gate stack having the multi-layer molybdenum structure Fig 2E, 214 ¶0044 on a second gate dielectric Fig 2E, 209. Ouellette discloses all the limitations but silent on a multi-layer molybdenum structure for the PMOS gate stack. Whereas Cheng discloses a PMOS gate stack having a multi-layer molybdenum structure Fig 19A-19F ¶0026, 0081-0082. While Park discloses a conductive fill on the multi-layer molybdenum structure, the conductive fill separate and distinct from the multi-layer molybdenum structure ¶0087, 0092 Fig 15. Ouellette, Cheng and Park are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ouellette because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the material used for the PMOS device and incorporate the teachings of Cheng/Park
since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 12, Ouellette discloses comprising the multi-layer molybdenum structure on the second gate dielectric Fig 2E ¶0164 Claim 9.
Regarding claim 13, Ouellette discloses comprising the N-type conductive layer on the second gate dielectric Fig 2E ¶0164 Claim 9.
Regarding claim 14, Ouellette discloses: a memory coupled to the board Fig 9.
Regarding claim 15, Ouellette discloses a communication chip coupled to the board Fig 9.
Regarding claim 16, Ouellette discloses a battery coupled to the board Fig 9.
Regarding claim 17, Ouellette discloses a camera coupled to the board Fig 9.
Regarding claim 18, Ouellette discloses a display coupled to the board Fig 9.
Regarding claim 19, Ouellette discloses wherein the component is a packaged integrated circuit die Fig 9.
Regarding claim 20, Ouellette discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor Fig 9.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
