Prosecution Insights
Last updated: August 17, 2026
Application No. 18/129,688

BACKSIDE CONTACT ETCH BEFORE CAVITY SPACER FORMATION FOR BACKSIDE CONTACT OF TRANSISTOR SOURCE/DRAIN

Non-Final OA §103§112
Filed
Mar 31, 2023
Examiner
IMTIAZ, S M SOHEL
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
507 granted / 559 resolved
+22.7% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
47 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.2%
+22.2% vs TC avg
§102
17.2%
-22.8% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 559 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to applicant’s Restriction/Election filed on 06/29/2026. Currently claims 1-20 are pending in the application. Election/Restrictions Applicant's election without traverse of Group I, claims 1-14, in the reply filed on 06/29/2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/02/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner. Claim Rejections - 35 USC § 112 (b) The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 9-14 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention. Regarding claim 9, the instant claim recites “a backside contact extending through the substrate and in contact with one of the source or the drain,” and subsequently recites “wherein a portion of the spacer material is in contact with and between a portion of the backside contact and a portion of the source or the drain.” It is unclear whether “the source or the drain” in the wherein clause refers to the previously recited “one of the source or the drain” that is contacted by the backside contact, or to either of the source and the drain generally. Under the latter reading, the claim would encompass an arrangement in which the spacer material is between the backside contact and the terminal that the backside contact does not contact, rendering the metes and bounds of the claim unclear. For purposes of examination, the limitation is interpreted as “a portion of the one of the source or the drain.” Claims 10-14 are also rejected due to their dependence on a rejected base claim. Furthermore, regarding claims 11 and 12, each claim recites “a second portion of the source or the drain,” which is indefinite for the reasons set forth with respect to claim 9. The limitation is interpreted as “a second portion of the one of the source or the drain.” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0268344 A1 (Huang). Regarding claim 1, Huang discloses, an apparatus (Figs. 19A–19B; [0064]–[0071]), comprising: one or more semiconductor structures (124; second semiconductor layers; Fig. 19B; [0064]) over a substrate (330 over a base material is the substrate; Fig. 19B; [0064]) and extending between a source structure and a drain structure (240 on both sides; Fig.19B; [0064]), at least one of the source structure or the drain structure epitaxial to the one or more semiconductor structures ([0064]); Note on claim interpretation: Under the broadest reasonable interpretation, a “substrate” is a body or layer of material that supports the device structures. In Huang’s completed device, the original semiconductor substrate 110 is removed from the backside and replaced by isolation materials 330 (Figs. 15–18A; [0056] – [0057]), which thereafter support the device and through which the backside via extends. PNG media_image1.png 575 560 media_image1.png Greyscale a gate structure (260; gate structure; Fig. 19B; [0064]) adjacent to one or more channel regions (channel region is formed in layer 124) of the one or more semiconductor structures (124); a spacer material (210; inner spacer; ; Fig. 19B; [0068]) between the gate structure (260) and the at least one of the source structure or the drain structure (240); and a backside contact metal (350/360; backside metal alloy layer/backside via; Fig. 19B; [0062] – [0063]) extending through the substrate and in contact with the at least one of the source structure or the drain structure (240), and a portion of the at least one of the source structure or the drain structure (240) (element 340 contacts both 360 and 240). But Huang does not disclose explicitly that a portion of the spacer material is in contact with and between a portion of the backside contact metal and a portion of the at least one of the source structure or the drain structure. In Huang, a backside contact etch stop layer (CESL) 340, formed of a dielectric material such as Si₃N₄ or oxynitrides, conformally lines the backside contact opening 332 and the recesses 334 formed adjacent the inner spacers 210, such that the CESL 340 — rather than the inner spacers 210 — contacts the backside via 360; Huang expressly discloses that the CESL 340 “includes a portion having a greater width in contact with the inner spacer 210” (FIG. 19B; [0059] – [0062]). The CESL 340, being a dielectric, is not part of the backside contact metal. However, Huang teaches partially removing the inner spacers 210 to form recesses 334 adjacent the inner spacers, thereby widening the backside contact opening in the region adjoining the source epitaxial structure 240 (FIG. 18B; [0058]), and teaches removing the horizontal portion of the CESL 340 to expose the source 240 for formation of the backside metal alloy layer 350 by a self-aligned silicide process, followed by formation of the backside via 360 of W, Co, Ru, Al, or Cu ([0062] – [0063]). The CESL 340 is described as a feature of some embodiments and serves as an etch-stop liner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to omit the backside CESL 340, or to remove it from within the contact opening 332 and the recesses 334, such that the backside metal alloy layer 350 and backside via 360 are formed directly in the opening 332 and the recesses 334 and directly contact the inner spacers 210. In the resulting structure, a portion of the bottommost inner spacer 210 is in contact with and between a portion of the backside contact metal (350/360 filling the recess 334) and a portion of the source structure 240. One of ordinary skill would have been motivated to make this modification to enlarge the silicide contact area and reduce backside contact resistance, and the omission of an optional dielectric liner, with retention of its surrounding structures, is a predictable variation requiring only routine skill and yielding no more than expected results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416–17 (2007); MPEP 2143 (I)(A), (G). The modification would not render Huang unsatisfactory for its intended purpose, because the inner spacers 210 are themselves dielectric (silicon nitride-based; [0031]) and continue to insulate the gate structure 260 from the backside contact metal. Regarding claim 2, Huang discloses, the apparatus of claim 1, wherein the spacer material (210) comprises a continuous monolithic material portion (it is monolithic as shown in Fig. 19B) in contact with the gate structure (260, left), the portion of the backside contact metal (350/360/340), and the portion of the at least one of the source structure or the drain structure (240). Regarding claim 3, Huang discloses, the apparatus of claim 2, wherein the spacer material (210 on the right side) comprises a second continuous monolithic material portion in contact with a second gate structure (260, right), a second portion (right side portion) of the backside contact metal (350/360/340), and a second portion (right side portion) of the at least one of the source structure or the drain structure (240) (as evident in Fig. 19B). Regarding claim 4, Huang discloses, the apparatus of claim 2, wherein the spacer material (210 on the right side) comprises a second continuous monolithic material portion in contact with the gate structure and a second portion of the at least one of the source structure or the drain structure, wherein the second continuous monolithic material portion is vertically aligned with the continuous monolithic material portion (as evident in Fig. 19B). Regarding claim 5, Huang discloses, the apparatus of claim 1, wherein the spacer material (210) comprises silicon and one or more of oxygen, nitrogen, and carbon (silicon nitride; [0031]). Regarding claim 6, Huang discloses, the apparatus of claim 1, wherein the backside contact metal comprises one of titanium or tungsten (tungsten; [0063]). Regarding claim 7, Huang discloses, the apparatus of claim 1, wherein the backside contact metal (350/360) is in contact with the source structure (240 at the center), the apparatus further comprising a frontside contact metal (270/280; on left and right; Fig. 21B; [0047]) in contact with the drain structure (240 on left and right). PNG media_image2.png 702 516 media_image2.png Greyscale Regarding claim 8, Huang discloses, the apparatus of claim 1, wherein the one or more semiconductor structures (124) comprises a plurality of vertically aligned nanoribbons or nanosheets ([0013]). Claim 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0268344 A1 (Huang) and further in view of US 2022/0123134 A1 (Anderson). Regarding claim 9, Huang discloses, a system, comprising: PNG media_image3.png 575 564 media_image3.png Greyscale an integrated circuit (IC) die (Fig. 19B shows two transistors, therefore, it is an integrated circuit; [0064] – [0071]) comprising a transistor, the transistor comprising: a stack of nanoribbons (124 contains nanowires; [0013]) over a substrate, and coupled to a source and a drain (240) each epitaxial ([0064]) to the stack of nanoribbons (124 contains nanowires); a gate structure (260; gate structure; Fig. 19B; [0064]) on channel regions of the nanoribbons; a spacer material (210; inner spacer; ; Fig. 19B; [0068]) between the gate structure (260) and each of the source and the drain (240); and a backside contact (350/360; backside metal alloy layer/backside via; Fig. 19B; [0062]) extending through the substrate and in contact with one of the source or the drain (240), wherein a portion of the spacer material (210) is between a portion of the backside contact (350/360) and a portion of the source or the drain (240); But Huang does not disclose explicitly that a portion of the spacer material is in contact with and between a portion of the backside contact metal and a portion of the at least one of the source structure or the drain structure. In Huang, a backside contact etch stop layer (CESL) 340, formed of a dielectric material such as Si₃N₄ or oxynitrides, conformally lines the backside contact opening 332 and the recesses 334 formed adjacent the inner spacers 210, such that the CESL 340 — rather than the inner spacers 210 — contacts the backside via 360; Huang expressly discloses that the CESL 340 “includes a portion having a greater width in contact with the inner spacer 210” (FIG. 19B; [0059] – [0062]). The CESL 340, being a dielectric, is not part of the backside contact metal. However, Huang teaches partially removing the inner spacers 210 to form recesses 334 adjacent the inner spacers, thereby widening the backside contact opening in the region adjoining the source epitaxial structure 240 (FIG. 18B; [0058]), and teaches removing the horizontal portion of the CESL 340 to expose the source 240 for formation of the backside metal alloy layer 350 by a self-aligned silicide process, followed by formation of the backside via 360 of W, Co, Ru, Al, or Cu ([0062] – [0063]). The CESL 340 is described as a feature of some embodiments and serves as an etch-stop liner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to omit the backside CESL 340, or to remove it from within the contact opening 332 and the recesses 334, such that the backside metal alloy layer 350 and backside via 360 are formed directly in the opening 332 and the recesses 334 and directly contact the inner spacers 210. In the resulting structure, a portion of the bottommost inner spacer 210 is in contact with and between a portion of the backside contact metal (350/360 filling the recess 334) and a portion of the source structure 240. One of ordinary skill would have been motivated to make this modification to enlarge the silicide contact area and reduce backside contact resistance, and the omission of an optional dielectric liner, with retention of its surrounding structures, is a predictable variation requiring only routine skill and yielding no more than expected results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416–17 (2007); MPEP 2143 (I)(A), (G). The modification would not render Huang unsatisfactory for its intended purpose, because the inner spacers 210 are themselves dielectric (silicon nitride-based; [0031]) and continue to insulate the gate structure 260 from the backside contact metal. Furthermore, Huang fails to teach explicitly, a power supply coupled to the IC die. However, in analogous art, Anderson discloses, a power supply coupled to the IC die ([0028]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Huang and Anderson before him/her, to modify the teachings of an integrated circuit device as taught by Huang and to include the teachings of a power supply coupled to the IC die as taught by Anderson since the semiconductor device needs to be powered up and absent this important teaching in Huang, a person with ordinary skill in the art would be motivated to reach out to Anderson while forming an integrated circuit device of Huang. Regarding claim 10, Huang discloses, the system of claim 9, wherein the spacer material (210) comprises a continuous material portion (it is monolithic as shown in Fig. 19B) in contact with the gate structure (260, left), the portion of the backside contact (350/360), and the portion of the source or the drain (240). Regarding claim 11, Huang discloses, the system of claim 10, wherein the spacer material (210 on the right side) comprises a second continuous monolithic material portion in contact with a second gate structure (260, right), a second portion (right side portion) of the backside contact (350/360), and a second portion (right side portion) of the at least one of the source or the drain (240) (as evident in Fig. 19B). Regarding claim 12, Huang discloses, the system of claim 10, wherein the spacer material (210 on the right side) comprises a second continuous material portion in contact with the gate structure and a second portion of the source or the drain, wherein the second continuous material portion is vertically aligned with the continuous material portion (as evident in Fig. 19B). Regarding claim 13, Huang discloses, the system of claim 9, wherein the spacer material (210) comprises silicon and one or more of oxygen, nitrogen, and carbon, (silicon nitride; [0031]) and the backside contact comprises one of titanium or tungsten (tungsten; [0063]). Regarding claim 14, Huang discloses, the system of claim 9, wherein the backside contact (350/360) is in contact with the source (240 at the center), the transistor further comprising a frontside contact (270/280; on left and right; Fig. 21B; [0047]) in contact with the drain (240 on left and right). PNG media_image2.png 702 516 media_image2.png Greyscale Examiner’s Note (Additional Prior Arts) The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure. US 2024/0266409 A1 (Kang) - A method of forming backside source/drain contact is disclosed. The method includes forming a dummy contact structure in a substrate, the dummy contact structure having a central portion and a side portion, the central portion being higher than the side portion to have a height above the substrate; forming a source/drain region of a first transistor and a second transistor above the dummy contact structure, the first and second transistors being above the substrate; removing the dummy contact structure from a backside of the substrate to create a backside contact opening; and forming a backside source/drain contact by filling the backside contact opening with a conductive material. Structure of the backside source/drain contact formed thereby is also provided. US 2024/0096699 A1 (Zhang) - A semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer and a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below gate spacers of the nanosheet transistor. The backside contact is closer to a backside of the wafer than a frontside of the wafer. The dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor. US 2023/0317809 A1 (Naskar) - A semiconductor device is disclosed comprising a substrate, and a non-planar transistor with a source and a drain over the substrate. In an embodiment, a backside contact is provided to the source or drain through the substrate. In an embodiment, a residual liner is between the source or drain and the backside contact. In an embodiment, the residual liner does not extend entirely across an interface between the backside contact and the source or drain. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S M SOHEL IMTIAZ/Primary Patent Examiner Art Unit 2812 07/10/2026
Read full office action

Prosecution Timeline

Mar 31, 2023
Application Filed
Aug 30, 2023
Response after Non-Final Action
Jul 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
98%
With Interview (+6.9%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 559 resolved cases by this examiner. Grant probability derived from career allowance rate.

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