Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Kirby et al. (US 20070045858 A1) in view of Lee et al. (US 20100013061 A1) and/or Lake (US 20060292877 A1).
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CLAIM 1. Kirby teaches an apparatus, comprising:
a die 212 (Fig. 3G & ¶141) comprising:
a dielectric portion 233 comprising a dielectric die edge sidewall having a sidewall profile comprising a substantially continuous sidewall slope; and
a bulk silicon portion 212 on the dielectric portion 233 (e.g. Location where dielectric sidewall and bulk substrate openings meet.), the bulk silicon portion comprising a bulk silicon die edge sidewall in substantial alignment with the dielectric die edge sidewall (Fig. 3G),wherein a portion of the bulk silicon die edge sidewall a plurality of scalloped regions [345c-e…] along a vertical distance thereof (Fig. 3G); and
an interface region between the dielectric die edge sidewall and the plurality of scalloped regions, wherein the dielectric die edge sidewall comprises a substantially vertical sidewall and the bulk silicon die edge sidewall in the interface region (Note: The claim does not define the depth/distance of the interface region. At a very small finite size, the surface may be considered vertical.) comprises a substantially vertical sidewall, wherein the dielectric die edge sidewall and the bulk silicon die edge sidewall in the interface region are colinear.
As noted above, having some finite distance considered vertical at the silicon die sidewall edge top interface is at least a obvious expectation to a PHOSITA. The claim does not define the actual depth or scale. Etching is not perfect and will cause surface roughness which at a very small scall may not be considered “substantially vertical” but at a larger scale would be considered “substantially vertical.” Further, even in Kirby, the small finite uppermost portion of the bulk substrate at the surface point has a finite point which could be considered “substantially vertical” under BRI.
Demonstrating the capability more clearly see Lee and Lake. As shown in Lee, mask formation can dictate initial sidewall profile when etching scalloped regions to form a trench in a bulk substrate. As shown in fig. 4A-8D, a mask for Isotropic etching may include a mask that overhangs the sidewall, thereby allowing for the scalloping to occur at a depth relative the uppermost surface.
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Lake, alternatively performs a series of isotropic etching steps to effectively create a substantially vertical profile at the top region of the trench, (Fig. 4A).
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In view of Kirby, Lee, and/or Lake, simply modifying the structure to of Kirby or describing Kirby to have a substantially vertical sidewall profile at the interface region.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the interface region such that some finite portion of the silicon and dielectric may be considered substantially colinear and vertical, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 2. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, wherein the plurality of scalloped regions comprise a plurality of vertically adjacent concave notches (Fig. 3G )within the bulk silicon die 212 edge sidewall (Fig. 3G).
CLAIM 3. Kirby in view of Lee and/or Lake teaches the apparatus of claim 2, however may be wherein individual vertically adjacent concave notches of the plurality of vertically adjacent concave notches comprise a lateral width of between 0.2 microns to 5 microns.
Kirby does however teach in paragraph 13 “such microfeature workpieces have critical dimensions2 less than or equal to 1 [micrometer], and in many applications the critical dimensions of the smaller features are less than 0.25 [micrometer]or even less than 0.1 [micrometer]”. As such, it would be at least obvious to a PHOSITA the critical dimension of the openings (lateral width/diameter) to be withing the claimed range.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the “lateral width” through routine experimentation and optimization to obtain optimal or desired device performance because the “lateral width” is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIMS 4 &13. Kirby in view of Lee and/or Lake teaches the system of claim 12, wherein an interface region is free of the concave notch/regions (Fig. 2E – 233-dielectric, 230 interface sidewall, 212- concave regions.).
Alternatively, modifying Kirby in light of Lee et al. would be obvious to a PHOSITA. As demonstrated in Lee et al. Figure 9B, it is a known, capable technique to form a vertical silicon sidewall that is free of concave regions at the dielectric interface. Lee further teaches that any corresponding concave regions can be positioned at a finite distance from the bulk substrate surface, providing a clear motivation to modify Kirby to eliminate these regions at the critical interface.
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When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
CLAIM 5. Kirby in view of Lee and/or Lake teaches the apparatus of claim 4, wherein individual ones of the plurality of vertically adjacent concave notches that are closer to the interface region comprise a greater lateral width than a lateral width of individual ones of the plurality of vertically adjacent concave notches that are farther from the interface region (Fig. 2E).
CLAIM 6. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, wherein one or more devices are adjacent to the dielectric die edge sidewall and over the bulk silicon portion (Fig. 2P – IC – A PHOSITA would recognize the capability of one or more devices adjacent the structure. IC circuits may comprise one to a large number of devices.).
CLAIM 7. Kirby in view of Lee and/or Lake teaches the apparatus of claim 6, wherein the one or more devices comprise a transistor (Fig. 2P – IC – A PHOSITA would recognize the capability of one or more devices adjacent the structure. IC circuits may comprise one to a large number of devices. Transistors are fundamental and common feature of IC circuits. Event though Kirby is silent upon transistors, a PHOSITA would understand or expect the inclusion of transistors in the disclosed IC. As such, transistors would be a obvious modification to the IC of Kirby if not already present by a PHOSITA at the time of the invention.).
CLAIM 8. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, wherein the dielectric portion 232/230comprises at least one of oxygen, nitrogen, silicon nitride, or a silicon oxide material (Fig. 2O - ¶153 – 232/230- SiO/SiN).
CLAIM 9. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, wherein the dielectric die edge sidewall is free of metal (Fig. 2O - ¶15,22 – 232/230- SiO/SiN, 234 - SiO).
CLAIM 10. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, wherein the dielectric die edge sidewall 230 is free of scalloped regions (Figs. 2E, 2F, 3G, etc..).
CLAIM 11. Kirby in view of Lee and/or Lake teaches the apparatus of claim 1, however does not depict wherein the die is on a package substrate. Kirby teaches in paragraph 2, the “ dies are separated from each other and packaged to form individual microelectronic devices that can be attached to modules or installed in other products.” In packaging it is a understanding that the die will be on a package substrate. Further, attaching to a module or installing in other products will also be underdressed to include placing the die “on” a substrate, meeting the broad scope of the “apparatus” claim.
CLAIM 12. Kirby in view of Lee and/or Lake teaches a system, comprising:
a substrate (Kirby teaches in paragraph 2, the “ dies are separated from each other and packaged to form individual microelectronic devices that can be attached to modules or installed in other products.” In packaging it is a understanding that the die will be on a package substrate. Further, attaching to a module or installing in other products will also be underdressed to include placing the die “on” a substrate, meeting the broad scope of the “apparatus” claim.);
a die 212 on the substrate (¶2).
the die comprising:
a dielectric portion 230 comprising a dielectric die edge sidewall between 0 degrees to 20 degrees of a vertical profile (Fig. 2O/3G); and
a bulk silicon portion 212 on the dielectric portion 230, wherein a bulk silicon die 212 edge sidewall comprises four concave regions along a vertical distance of the bulk silicon die edge sidewall (Fig. 2O).
Kirby may be silent upon wherein a lateral offset between the dielectric die edge sidewall and the bulk silicon sidewall is less than 2 percent of a vertical profile.
The figures of Kirby however demonstrate the scalloped sidewall opening meet and are aligned with the dielectric opening. Being aligned a PHOSITA would recognize would be off set by zero percent, therefore one would expect to at least try for a zero offset.
Further the percent offset would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the offset through routine experimentation and optimization to obtain optimal or desired device performance because the offset is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
CLAIM 14. Kirby in view of Lee and/or Lake teaches the system of claim 12, however may be wherein individual vertically adjacent concave notches of the plurality of vertically adjacent concave notches comprise a lateral width of between 0.2 microns to 5 microns.
Kirby does however teach in paragraph 13 “such microfeature workpieces have critical dimensions less than or equal to 1 [micrometer], and in many applications the critical dimensions of the smaller features are less than 0.25 [micrometer]or even less than 0.1 [micrometer]”. As such, it would be at least obvious to a PHOSITA the critical dimension of the openings (lateral width/diameter) to be withing the claimed range.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the “lateral width” through routine experimentation and optimization to obtain optimal or desired device performance because the “lateral width” is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
CLAIM 15. Kirby in view of Lee and/or Lake teaches the system of claim 14, wherein the dielectric portion comprises one or more transistors, wherein the one or more transistors are over the bulk silicon portion and are adjacent to the plurality of concave regions (Fig. 2P – IC – A PHOSITA would recognize the capability of one or more devices adjacent the structure. IC circuits may comprise one to a large number of devices. Transistors are fundamental and common feature of IC circuits. Event though Kirby is silent upon transistors, a PHOSITA would understand or expect the inclusion of transistors in the disclosed IC. As such, transistors would be a obvious modification to the IC of Kirby if not already present by a PHOSITA at the time of the invention.).
CLAIM 16. Kirby in view of Lee and/or Lake teaches the system of claim 12, however may be silent upon wherein a power supply is coupled to the die. It is fundamental understanding semiconductor devices operate using electricity, thereby requiring a power supply. As such, it would be obvious to a PHOSITA to connect the die to a power supply to create the system of claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/24/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Kirby - [0014] FIGS. 2A-2Q illustrate stages of a method for forming interconnects in a microfeature workpiece 200 in accordance with an embodiment of the invention. FIG. 2A, for example, is a side cross-sectional view of a portion of the workpiece 200 at an initial stage before the interconnects have been formed. The workpiece 200 can include a substrate 212 and a plurality of microelectronic dies 220 formed in and/or on the substrate 212. The substrate 212 has a first side 214 and a second side 216 opposite the first side 214. The substrate 212 is generally a semiconductor wafer, and the dies 220 are arranged in a die pattern on the wafer. The individual dies 220 include integrated circuitry 221 (shown schematically) and a plurality of terminals 222 (e.g., bond-pads) electrically coupled to the integrated circuitry 221. The terminals 222 shown in FIG. 2A are external features at the first side 214 of the substrate 212. In other embodiments, however, the terminals 222 can be internal features that are embedded at an intermediate depth within the substrate 212.
2 Kirby - [0013] Specific details of several embodiments of the invention are described below with reference to interconnects extending from a terminal proximate to the front side of a workpiece, but the methods and interconnects described below can be used for other types of interconnects within microelectronic workpieces. Several details describing well-known structures or processes often associated with fabricating microelectronic devices are not set forth in the following description for purposes of clarity. Also, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the elements shown and described below with reference to FIGS. 2A-3G. The term "microfeature workpiece" is used throughout to include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, and other features are fabricated. For example, microfeature workpieces can be semiconductor wafers, glass substrates, dielectric substrates, or many other types of substrates. Many features on such microfeature workpieces have critical dimensions less than or equal to 1 .mu.m, and in many applications the critical dimensions of the smaller features are less than 0.25 .mu.m or even less than 0.1 .mu.m. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word "or" is expressly limited to mean only a single item exclusive from other items in reference to a list of at least two items, then the use of "or" in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term "comprising" is used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or types of other features and components are not precluded.
3 Kirby - [0015] FIG. 2B is a side cross-sectional view of the area 2B shown in FIG. 2A. In previous processing steps, a first dielectric layer 230 was applied to the first side 214 of the substrate 212, and a second dielectric layer 232 was applied over the first dielectric layer 230. The second dielectric layer 232 was then patterned and etched to expose the terminal 222. The dielectric layers 230 and 232 can be a polyimide material or other suitable nonconductive materials. For example, the dielectric layers 230 and 232 can be parylene, a low temperature chemical vapor deposition (low temperature CVD) material such as silicon nitride (Si.sub.3N.sub.4), silicon oxide (SiO.sub.2), and/or other suitable materials. The foregoing list of dielectric materials is not exhaustive. The dielectric layers 230 and 232 are generally not composed of the same material as each other, but these layers may be composed of the same material. In addition, one or both of the layers 230 and 232 may be omitted and/or additional layers may be included. After depositing the second dielectric layer 232, a mask 233 is applied over the second dielectric layer 232 and patterned as shown in FIG. 2B. The mask 233 can be a layer of resist that is patterned according to the arrangement of terminals 222 on the workpiece 200. As such, the mask 233 has an opening over the terminal 222.
Prosecution Insights