DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/01/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Amendment
Applicant's Amendment filed 05/01/2026 has been fully considered and entered.
The examiner notes the Summary of the Examiner Interview on page 1 recites: “During the interview, it was agreed that claims 1 and 12 overcome the current references.” The examiner notes that “the claims” refers to the claim amendments proposed during the interview.
The objection to the claims, which were set forth in the Office Action mailed 02/23/2026, have been withdrawn in view of Applicant’s Amendment.
The rejection under 35 U.S.C. 112(b) set forth in the Office Action mailed 02/23/2026 is withdrawn in view of Applicant’s Amendment.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwaki et al. in US 20040001661 A1 (hereinafter "Iwaki").
Regarding claim 1, Iwaki discloses a semiconductor package, comprising:
a first electronic element disposed over a first substrate (optical emitter 101 is interpreted as the first electronic element; the light transmitting resin 109 disposed over, under, and around 101 is interpreted as the first substrate);
a second electronic element disposed over a second substrate spaced apart from the first substrate (optical receiver 103 is interpreted as the second electronic element; the light transmitting resin 109 disposed over, under, and around 103 is interpreted as the second substrate; the two portions of 109 can be seen spaced apart from each other in Fig. 8);
a first interconnection element connected to the first electronic element and the second electronic element (the waveguide core 105 is interpreted as the first interconnection element; 105 optically connects 101 and 103 as seen in Fig. 8); and
a monolithic cladding structure entirely covering the first interconnection element (waveguide cladding 106 is interpreted as the monolithic cladding structure; 106 can be seen completely covering 105 in Fig. 8),
wherein the monolithic cladding structure directly contacts a first lateral surface of the first substrate facing the second substrate and a second lateral surface of the second substrate facing the first substrate (the interpreted monolithic cladding structure 106 directly contacts the lateral surfaces of 109 of 101 and 103 facing each other; see Fig. 8);
wherein the first interconnection element is configured to optically transmit a signal between the first electronic element and the second electronic element (waveguide core 105 interpreted as the first interconnection element necessarily transmits optical signals; see Para. [0003], [0019] and [0034]);
wherein the first electronic element comprises a first electrical bump connected to the first substrate (the wiring pattern 121 touching 101, 109, and 106 in Fig. 8 is interpreted as the first electrical bump) and the second electronic element comprises a second electrical bump connected to the second substrate (the wiring pattern 121 touching 103, 109, and 106 in Fig. 8 is interpreted as the second electrical bump); and
wherein the monolithic cladding structure covers the first electrical bump and/or the second electrical bump (106 is seen covering the underside of 121 touching 103, 109, and 106 in the orientation shown in Fig. 8).
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Claim(s) 12-13, 15, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yonekura et al. in US 20080279518 A1 (hereinafter "Yonekura").
Regarding claim 12, Yonekura discloses a semiconductor package, comprising:
a first electronic element disposed over a first substrate (light emitting element 203 is interpreted as the first electronic element; pad portion 241 is interpreted as the first substrate since it helps support 203; see Fig. 1-2 where 203 is shown disposed over 241), wherein the first electronic element has an active surface facing the first substrate (the surface of 203 containing light emitting portion 262 is interpreted as the active surface and faces 241; see Fig. 1-2), and wherein the active surface of the first electronic element has a first portion non-overlapped with the first substrate vertically (Fig. 2 has R1 which clearly indicates that that 203 creates an overhang that has the interpreted active surface of 203 having a right-hand portion interpreted as the first portion non-overlapped with 241 vertically; see also Fig. 1);
a second electronic element disposed over a second substrate spaced apart from the first substrate (light-receiving element 204 is interpreted as the second electronic element; pad portion 242 is interpreted as the second substrate since it helps support 204; see Fig. 1 where 204 is shown disposed over 242), wherein the second electronic element has an active surface facing the second substrate (the surface of 204 containing light receiving portion 267 is the active surface of 204 and faces 242; see Fig. 1),
wherein the active surface of the second electronic element has a second portion non-overlapped with the second substrate vertically (mirrored version of Fig. 2; see Fig. 1; note that a portion of 204 does not overlap with 242 vertically); and
a first interconnection element connected to the first portion of the first electronic element and the second portion of the second electronic element (the core portion 256 is interpreted as the first interconnection element optically connected to the aforementioned first portion of 203 and the aforementioned second portion of 204; see Fig. 1),
wherein the first interconnection element is physically spaced apart from a base over which the first substrate and the second substrate are disposed (256 is physically spaced apart from substrate main body 211 interpreted as the base over which 241 and 242 are disposed; see Fig. 1).
Regarding claim 13, Yonekura discloses the semiconductor package of claim 12 as discussed above, wherein the first electronic element has an overhang extending beyond an edge of the first substrate, and an optical bump is disposed under the overhang (the vertically non-overlapped portion of 203 aforementioned is interpreted as the overhang extending beyond the edge of 241; light emitting portion 262 is interpreted as the optical bump disposed under the overhang; see Fig. 1-2).
Regarding claim 15, Yonekura discloses a semiconductor package, comprising:
a first electronic element disposed over a first substrate (light emitting element 203 is interpreted as the first electronic element; pad portion 241 is interpreted as the first substrate since it helps support 203; see Fig. 1-2 where 203 is shown disposed over 241), the first electronic element having an active surface facing the first substrate (the surface of 203 containing light emitting portion 262 is interpreted as the active surface and faces 241; see Fig. 1-2), wherein the active surface of the first electronic element has a first portion non-overlapping the first substrate vertically and a second portion overlapping the first substrate vertically (Fig. 2 has R1 which clearly indicates that that 203 creates an overhang that has the interpreted active surface of 203 having a right-hand portion interpreted as the first portion non-overlapped with 241 vertically and a left-hand portion interpreted as the second portion overlapping 241 vertically; see also Fig. 1), wherein the first portion of the first electronic element is configured for optical transmission (the right-hand portion has light emitting portion 262 which is capable of optical transmission; see Fig. 1-2 and see Para. 18) and the second portion of the first electronic element is configured for electrical transmission (the left-hand portion has terminal 261 which is capable of electrical transmission; see Fig. 1-2 and see Para. 18); and
a second electronic element disposed over a second substrate spaced apart from the first substrate (light-receiving element 204 is interpreted as the second electronic element; pad portion 242 is interpreted as the second substrate since it helps support 204; see Fig. 1 where 204 is shown disposed over 242), the second electronic element having an active surface facing the second substrate (the surface of 204 containing light receiving portion 267 is the active surface of 204 and faces 242; see Fig. 1), wherein the active surface of the second electronic element has a first portion non-overlapping the second substrate vertically and a second portion overlapping the second substrate vertically (mirrored version of Fig. 2; see Fig. 1; note that a left-hand portion of 204 does not overlap with 242 vertically and a right-hand portion of 204 overlaps with 242 vertically), wherein the first portion of the second electronic element is configured for optical transmission (the left-hand portion of 204 has light receiving portion 267 which is capable of optical transmission; see Fig. 1-2 and see Para. 18) and the second portion of the second electronic element is configured for electrical transmission (the right-hand portion has terminal 266 which is capable of electrical transmission; see Fig. 1-2 and see Para. 18).
Regarding claim 18, Yonekura discloses the semiconductor package of claim 15 as discussed above, further comprising:
a first interconnection element connected to the first portion of the first electronic element for optical transmission (mirror 253 is interpreted as a first interconnection element connected to the first portion of 203 and is capable of optical transmission; the mirror is connected and interconnected to many elements in the system); and
a second interconnection element connected to the first portion of the second electronic element for optical transmission (mirror 254 is interpreted as a second interconnection element connected to the first portion of 204 and is capable of optical transmission; the mirror is connected and interconnected to many elements in the system), wherein the first interconnection element and the second interconnection element are physically spaced apart from a base over which the first substrate and the second substrate are disposed (253 and 254 are physically spaced apart from substrate main body 211 interpreted as the base over which 241 and 242 are disposed; see Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 21, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yonekura et al. in US 20080279518 A1 (hereinafter "Yonekura") as applied above, and in view of Ohtsu et al. in US 20100021119 A1 (hereinafter "Ohtsu") .
Regarding claim 1, Yonekura discloses a semiconductor package, comprising:
a first electronic element disposed over a first substrate (light emitting element 203 is interpreted as the first electronic element; pad portion 241 is interpreted as the first substrate since it helps support 203; see Fig. 1-2 where 203 is shown disposed over 241);
a second electronic element disposed over a second substrate spaced apart from the first substrate (light-receiving element 204 is interpreted as the second electronic element; pad portion 242 is interpreted as the second substrate since it helps support 204; see Fig. 1 where 204 is shown disposed over 242);
a first interconnection element connected to the first electronic element and the second electronic element (the core portion 256 is interpreted as the first interconnection element optically connected to 203 and 204; see Fig. 1); and
wherein the first interconnection element is configured to optically transmit a signal between the first electronic element and the second electronic element (the core portion 256 is capable of optical signal transmission between light emitting portion 203 and light receiving portion 204);
wherein the first electronic element comprises a first electrical bump connected to the first substrate (203 has terminal 261 which is interpreted as the first electrical bump connected to 241) and the second electronic element comprises a second electrical bump connected to the second substrate (204 has terminal 262 which is interpreted as the second electrical bump connected to 242).
Yonekura fails to disclose the combination where:
a monolithic cladding structure entirely covering the first interconnection element,
wherein the monolithic cladding structure directly contacts a first lateral surface of the first substrate facing the second substrate and a second lateral surface of the second substrate facing the first substrate; and
wherein the monolithic cladding structure covers the first electrical bump and/or the second electrical bump.
Ohtsu teaches:
a monolithic cladding structure entirely covering the first interconnection element (flame retardant resin 13 is interpreted as the monolithic cladding structure which entirely covers optical waveguide film 10 which is interpreted as a first interconnection element),
wherein the monolithic cladding structure directly contacts a first lateral surface of the first substrate facing the second substrate and a second lateral surface of the second substrate facing the first substrate (when Ohtsu’s flame retardant resin 13 is used to cover all elements of Yonekura, the resultant structure of Yonekura/Ohtsu is such that the monolithic cladding structure directly contacts a first lateral surface of the first substrate facing the second substrate and a second lateral surface of the second substrate facing the first substrate); and
wherein the monolithic cladding structure covers the first electrical bump and/or the second electrical bump (when Ohtsu’s flame retardant resin 13 is used to cover all elements of Yonekura, it necessarily covers 261 and 262).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the flame retardant resin of Ohtsu as a monolithic cladding structure in the semiconductor package of Yonekura for the purpose of providing a covering over the structure thereby achieving increased protection, especially from flames.
Regarding claim 2, Yonekura/Ohtsu discloses the semiconductor package of claim 1 as discussed above, wherein the first electronic element comprises a first optical bump protruding from a surface of the first electronic element facing the first substrate (light emitting portion 262 is interpreted as the optical bump protruding from a surface of 203 facing 241), and the second electronic element comprises a second optical bump protruding from a surface of the second electronic element facing the second substrate (light receiving portion 267 is interpreted as the optical bump protruding from 204 facing 242), and wherein the first interconnection element is connected to the first optical bump and the second optical bump (256 is optically connected to 262 and 267).
Regarding claim 3, Yonekura/Ohtsu discloses the semiconductor package of claim 2 as discussed above, wherein a projection of the first substrate in a vertical direction exposes the first optical bump, and/or a projection of the second substrate in a vertical direction exposes the second optical bump (a projection of 241 and/or 242 in a vertical direction exposes 262 and/or 267 respectively since the projections help to raise the height of 203 and/or 204 respectively thus helping to permit access to the location of 262 and/or 267 respectively; this access is interpreted as exposure).
Regarding claim 21, Yonekura/Ohtsu discloses the semiconductor package of claim 2 as discussed above, wherein the monolithic cladding structure covers the first optical bump and the second optical bump (Ohtsu’s flame retardant resin 13 is interpreted as the monolithic cladding structure which entirely covers 262 and 267 when applied to Yonekura).
Regarding claim 24, Yonekura discloses the semiconductor package of claim 12 as discussed above, but fails to teach the combination such that:
a monolithic cladding structure entirely covering the first interconnection element,
wherein the monolithic cladding structure directly contacts a first portion of a first lateral surface of the first electronic element facing the second electronic element and a first portion of a second lateral surface of the second electronic element facing the first electronic element.
Ohtsu teaches:
a monolithic cladding structure entirely covering the first interconnection element (flame retardant resin 13 is interpreted as the monolithic cladding structure which entirely covers optical waveguide film 10 which is interpreted as a first interconnection element),
wherein the monolithic cladding structure directly contacts a first portion of a first lateral surface of the first electronic element facing the second electronic element and a first portion of a second lateral surface of the second electronic element facing the first electronic element (when Ohtsu’s flame retardant resin 13 is used to cover all elements, the resultant structure of Yonekura/Ohtsu is such that the monolithic cladding structure directly contacts a first portion of a first lateral surface of the first electronic element facing the second electronic element and a first portion of a second lateral surface of the second electronic element facing the first electronic element; see Fig. 13 of Ohtsu which shows that 13 covers upper and lateral surfaces of all elements including electronic elements such as light-emitting element 32 and light-receiving element 34).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the flame retardant resin of Ohtsu as a monolithic cladding structure in the semiconductor package of Yonekura for the purpose of providing a covering over the structure thereby achieving increased protection, especially from flames.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki et al. in US 20040001661 A1 (hereinafter "Iwaki").
Regarding claim 11, Iwaki discloses the semiconductor package of claim 1 as discussed above, but fails to explicitly teach that a length by which the first electronic element extends beyond an edge of the first substrate is different from a length by which the second electronic element extends beyond an edge of the second substrate.
However, it would have been an obvious matter of design choice to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the length by which the first electronic element extends beyond an edge of the first substrate be longer than the length by which the second electronic element extends beyond an edge of the second substrate in the device of Iwaki since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yonekura et al. Fig. 1-2 in US 20080279518 A1 (hereinafter "Yonekura 1") in view of Yonekura et al. Fig. 27 in US 20080279518 A1 (hereinafter "Yonekura 27").
Regarding claim 14, Yonekura 1 discloses the semiconductor package of claim 13 as discussed above, but fails to disclose that the embodiment of Fig. 1-2 teaches that the first interconnection element includes a photonic bonding wire or an optical fiber. However, Fig. 27 (Yonekura 27) teaches that optical fiber 151 may be included as a portion of the interconnection element. Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the selected the optical fiber of Fig. 27 of Yonekura 27 as the optical waveguide connection in the device of Yonekura 1 for the purpose of transmitting over great distances thereby achieving increased communication capability.
Allowable Subject Matter
Claims 7-10, 22-23, and 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, which is the most relevant prior art known, does not disclose or render obvious:
A semiconductor package as defined by claim 7, comprising:
a base over which the first substrate and the second substrate is disposed;
a first filling structure formed between the first substrate and the base;
a second filling structure formed between the second substrate and the base; and
an encapsulant covering the first electronic element and the second electronic element in combination with all of the other limitations of base claim 1; or
A semiconductor package as defined by claim 25, comprising:
an encapsulant directly contacting a second portion of the first lateral surface of the first electronic element and a second portion of the second lateral surface of the second electronic element,
wherein an interface between the encapsulant and the monolithic cladding structure comprises a concave surface recessed toward the monolithic cladding structure in combination with all of the other limitations of base claim 24.
The Iwaki, Yonekura, and/or Ohtsu reference(s) fail to disclose such limitations, and if modified to include the structures required by the limitations would fail to operate as intended. Nothing on the record suggests that such differences would be obvious to one having ordinary skill in the art before the effective filing date of the claimed invention. Lastly, one having ordinary skill in the art does not possess any general knowledge or known motivations to find such differences obvious in view of the prior art of record. As such, claims 8-10 and 22-23 are objected to as allowable by virtue of ultimate dependency upon claim 7. Claims 26-27 are objected to as allowable since they ultimately depend upon claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARBY M THOMASON whose telephone number is (703)756-5817. The examiner can normally be reached Mon.-Fri. 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARBY M. THOMASON/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
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