DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's Amendment filed 9/3/2025 has been fully considered and entered.
The objections to the specification and claim(s), which were set forth in the Office action mailed 06/04/2025, have been withdrawn in view of Applicant’s Amendment, however, a new objection is placed forth. See section below for details.
The rejection under 35 U.S.C. 112(b) set forth in the Office action mailed 10/24/2025 is withdrawn in view of Applicant’s Amendment, however, a new rejection is placed forth. See section below for details.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 7-15, 18, and 21-27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s).
Claim Objections
Claim 22 is objected to because of the following informalities:
A period needs to be added at the end of the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “in a way different” in claim 8 is a relative term which renders the claim indefinite. The term “in a way different” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Does “in a way different” mean any sort of difference? Is it attempting to imply that the transmission is also “in a way similar”? The examiner is interpreting the claim to mean any difference between the two signals transmissions (including, but not limited to, length, duration, type, amplitude, time, different end points or start parts, etc.) is enough to meet the claimed limitation. As such, the examiner is interpreting as if any difference between the two signal transmissions is sufficient and that no similarities are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-10, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pezeshki et al. in US 20220286211 A1 (hereinafter "Pezeshki").
Regarding claim 1, Pezeshki discloses a semiconductor package (semiconductor package; see Fig. 1A and Para. 30-33), comprising:
a first electronic element (optical transceiver chip 123a is interpreted as the first electronic element) disposed over a first substrate (interposer 115a is interpreted as the first substrate);
a second electronic element (optical transceiver chip 123b is interpreted as the second electronic element) disposed over a second substrate (interposer 115b is interpreted as the second substrate) spaced apart from the first substrate (interposer 115a is interpreted as the first substrate; see Fig. 1A where a gap exists between 115a and 115b);
a first interconnection element (multicore fiber 125 is interpreted as the first interconnection element) connected to the first electronic element and the second electronic element (see Fig. 1A where 125 connects 123a and 123b); and
wherein the first interconnection element (125) is configured to optically transmit a signal between the first electronic element and the second electronic element (see Para. 36 which discusses the optical transmission between the electronic elements).
Pezeshki further teaches in Fig. 2 and Para. 41 that the electronic elements (i.e., optical transceiver chip 211) can comprise electrical bumps (i.e., solder balls 215) connected to the substrate (i.e., interposer 213), thus Pezeshki’s device also teaches:
wherein the first electronic element comprises a first electrical bump connected to the first substrate and the second electronic element comprises a second electrical bump connected to the second substrate (present when the information of Fig. 2 is applied to each optical transceiver chip of Fig. 1); and
wherein the filling structure (package cover 117a and 117b is interpreted as the filling structure since they fill up space in the semiconductor package) covers the first electrical bump and/or the second electrical bump (117a covers the optical transceiver chip 123a and thus also covers the interpreted electrical bumps existing between the optical transceiver chip and the interposer; a similar interpretation is applied to 117b and the second electrical bump; see Fig. 1A and 2).
Regarding claim 7, Pezeshki discloses the semiconductor package of claim 1 as discussed above, and further comprising:
wherein the filling structure fills in at least a part of a gap between the first electronic element and the second electronic element and at least a part of a gap between the first substrate and the second substrate (package cover 117a and 117b exist and thus fill a part of the gap between the interpreted first electronic element 123a and the interpreted second electronic element 123b and at least a part of a gap between the interpreted first substrate 115a and the interpreted second substrate 115b; see Para. 32 and Fig. 1A).
Regarding claim 8, Pezeshki discloses the semiconductor package of claim 1 as discussed above. Pezeshki’s package in Fig. 1A further comprises a third electronic element (semiconductor chip 113a is interpreted as the third electronic element) disposed over the first substrate (115a), wherein a signal transmission between the third electronic element and the first electronic element (123a and 113a communicate electrically; see Para. 33) is in a way different from a signal transmission between the first electronic element and the second electronic element (123a and 123b communicate optically; see Para. 36).
Regarding claim 9, Pezeshki discloses the semiconductor package of claim 8 as discussed above, and further discloses wherein the third electronic element (113a) is electrically connected (see Para. 33) to the first electronic element (123a) through a second interconnection element (traces are interpreted as the second interconnection element; see Para. 33) of the first substrate (115a).
Regarding claim 10, Pezeshki discloses the semiconductor package of claim 8 as discussed above. Pezeshki further discloses the semiconductor package in Fig. 1A:
wherein a signal transmission path between the third electronic element and the first electronic element is shorter than a signal transmission path between the first electronic element and the second electronic element (the signal transmission path is physically shorter for on-module signal transmission than the signal transmission path between modules, thus the length of the traces is physically shorter than the length of multicore fiber 125; see also Fig. 1A and Para. 33).
Regarding claim 22, Pezeshki discloses the semiconductor package of claim 8 as discussed above, wherein the filling structure covers at least a part of a lateral surface of the first electronic element facing the third electronic element (117a is interpreted as covering the entirety of 123a, including all surfaces of 123a, and thus including at least a part of a lateral surface of 123a facing 113a).
Claim(s) 15, 18, and 24-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pezeshki et al. in US 20220286211 A1 (hereinafter "Pezeshki").
Regarding claim 15, Pezeshki discloses the semiconductor package, comprising:
a first electronic element disposed over a first substrate (optical transceiver chip 123a, which is interpreted as the first electronic element, disposed over interposer 115a, which is interpreted as the first substrate; see Fig. 1A);
a second electronic element disposed over a second substrate spaced apart from the first substrate (optical transceiver chip 123b, which is interpreted as the second electronic element, is disposed over interposer 115b, which is interpreted as the second substrate; see Fig. 1A);
a first interconnection element configured to optically transmit a signal between the first electronic element and the second electronic element (the cores of multicore fiber 125, which are interpreted as the first interconnection element, provides optical connection between 123a and 123b; see Para. 36 and Fig. 1A); and
a cladding material encapsulating the first interconnection element and being configured to confine light in the first interconnection element (125 contains cores and cladding material; the cladding material is interpreted as encapsulating the core and being configured to confine light in the core as is typical of optical fiber function; see Para. 56), and
wherein the semiconductor package further comprises
a base (circuit board 121 is interpreted as the base; see Para. 30 and Fig. 1A),
a first filling structure (the cover 117a and the package substrate 116a are interpreted as the first filling structure since they fill the area surrounding the module components) formed between the first substrate and the base (116a, interpreted as part of the filling structure, is formed between 115a and 121; see Fig. 1A), and
a second filling structure (the cover 117b and the package substrate 116b are interpreted as the first filling structure since they fill the area surrounding the module components) formed between the second substrate and the base (116b, interpreted as part of the filling structure, is formed between 115b and 121; see Fig. 1A); and
wherein the cladding material is disposed between the first filling structure and the second filling structure (the cladding material of 125 is interpreted as being disposed between part of the first filling structure 117a and part of the second filling structure 117b).
Regarding claim 18, Pezeshki discloses the semiconductor package of claim 15 as discussed above. Pezeshki’s package in Fig. 1A is further comprising a third electronic element (semiconductor chip 113a is interpreted as the third electronic element) disposed over the first substrate (115a), wherein the third electronic element (113a) is electrically connected (see Para. 33) to the first electronic element (123a) through a second interconnection element (traces are interpreted as the second interconnection element; see Para. 33) of the first substrate (115a).
Regarding claim 24, Pezeshki discloses the semiconductor package of claim 15 as discussed above, wherein the cladding material is in contact with the base (the cladding material of 125 is interpreted as being in thermal contact with all surrounding elements in the universe, including the base; the examiner notes that “contact” does not specify direct, physical contact between the components).
Regarding claim 25, Pezeshki discloses the semiconductor package of claim 15 as discussed above, wherein the cladding material is in contact with the first filling structure and the second filling structure (the cladding material of 125 is interpreted as being in thermal contact with all surrounding elements in the universe, including the first filling structure and the second filling structure; the examiner notes that “contact” does not specify direct, physical contact between the components).
Regarding claim 26, Pezeshki discloses the semiconductor package of claim 25 as discussed above, wherein an interface between the cladding material (the cladding material of optical fiber 125) and the first filling structure or the second filling structure (117a and/or 117b are interpreted as parts of the first filling structure and the second filling structure respectively) comprises a curved surface (the apertures 122a and 122b are interpreted as forming a curved surface since the outside of the fiber is curved and lies within either aperture).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 11, 21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki et al. in US 20220286211 A1 (hereinafter "Pezeshki") as applied above, and in view of Ecton et al. in US 20240176070 A1 (hereinafter "Ecton").
Regarding claim 2, Pezeshki discloses the semiconductor package of claim 1 as discussed above. Pezeshki further teaches:
wherein the first electronic element (123a) comprises a first optical bump (126) protruding from a surface of the first electronic element (see Fig. 1A where 126 protrudes from the top surface of 123a), and the second electronic element comprises a second optical bump protruding from a surface of the second electronic element (Para. 37 identifies the embodiment where direction changing coupling optics are also included in the second MCM, thus 126 would be replicated on and protrude from the top surface of optical transceiver chip 123b, wherein the direction changing coupling optics used with 123b are interpreted as the second optical bump), and wherein the first interconnection element is connected to the first optical bump and to the second optical bump (the interpreted optical bumps are optically connected with the multicore fiber 125 to enable chip-to-chip communication).
Pezeshki suggests that the fiber may be connected to the underside of the electronic elements (as in Fig. 12), but fails to explicitly teach:
the first optical bump facing the first substrate, and
the second optical bump facing the second substrate.
Ecton teaches that optical components (182) may be provided on the underside (see Fig. 1A) of electronic elements (PIC 104), such that they face a substrate (RDL 148-2). The examiner argues that Ecton’s arrangement may be used in the first and second module, such that:
the first optical bump protruding from a surface of the first electronic element facing the first substrate (Ecton’s optical component 182 protrudes from the surface of PIC 104 facing layer 148-2), and
the second optical bump protruding from a surface of the second electronic element facing the second substrate (Ecton’s optical component 182 protrudes from the surface of PIC 104 facing layer 148-2).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the optical bumps of Pezeshki protrude from the surface of the first and second electronic elements facing their respective substrates as taught by the arrangement of Ecton for the purpose of providing a better-protected attachment point during manufacturing thereby achieving a more reliable and durable optical connection and decreasing the overall rate of manufactured failures.
Regarding claim 3, Pezeshki/Ecton discloses the semiconductor package of claim 2 as discussed above. Pezeshki alone does not explicitly teach:
wherein a projection of the first substrate in a vertical direction exposes the first optical bump, and/or a projection of the second substrate in a vertical direction exposes the second optical bump.
Ecton teaches an arrangement:
wherein a projection of the first substrate in a vertical direction (the y-axis of Fig. 1A is interpreted as the vertical direction) exposes the first optical bump (because layer 148-2 only projects so far in the y-direction and does not fully cover 182, layer 148-2 is interpreted as exposing the location of 182; see Fig. 1A; when applied to Pezeshki, this results in an arrangement where 126 is not covered by 115a and is thus interpreted as being exposed). (The examiner notes that this arrangement is obvious in either the first or second module, and thus may also teach that a projection of the second substrate in a vertical direction exposes the second optical bump).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the arrangement of Ecton in the device of Pezeshki for the purpose of providing exposing the optical bump thereby achieving an easier point of fiber attachment for optical communication.
Regarding claim 11, Pezeshki discloses the semiconductor package of claim 1 as discussed above. Pezeshki fails to teach:
wherein a length by which the first electronic element extends beyond an edge of the first substrate is different from a length by which the second electronic element extends beyond an edge of the second substrate.
Ecton teaches an arrangement with an overhang (see Fig. 1A where the PIC 104 is interpreted as the electronic element and extends beyond the edge of the layer 148-2 which is interpreted as the substrate), thus Ecton teaches:
wherein a length by which the first electronic element extends beyond an edge of the first substrate and wherein a length by which the second electronic element extends beyond an edge of the second substrate (Ecton’s arrangement applied to both MCM modules would result in the interpreted first electronic element 123ab extending beyond the edge of the interpreted first substrate 115a and the interpreted second electronic element 123b extending beyond the edge of the interpreted second substrate 115b).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the arrangement of Ecton in the device of Pezeshki for the purpose of providing a point of attachment on the underside of the electronic element thereby achieving a more reliable and durable optical connection and decreasing the overall rate of manufactured failures.
Ecton fails to teach that the length of the first extension is longer than the length of the second extension.
Accordingly, it would have been an obvious matter of design choice to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the length by which the first electronic element extends beyond an edge of the first substrate be longer than the length by which the second electronic element extends beyond an edge of the second substrate in the device of Pezeshki/Ecton since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 21, Pezeshki/Ecton discloses the semiconductor package of claim 2 as discussed above, wherein the filling structure (117a and 117b) covers the first optical bump and the second optical bump (117a covers 126 and 117b covers 126 in the embodiment where 123b has 126 attached; see Para. 37 and note Fig. 1A).
Regarding claim 23, Pezeshki discloses the semiconductor package of claim 22 as discussed above, but fails to teach that the package further comprises:
an encapsulant covering the filling structure (117a and 117b),
wherein an interface between the filling structure (117a and 117b) and the encapsulant comprises a curved surface.
Ecton teaches an encapsulating mold covering many components that is interpreted as the encapsulant.
When Ecton’s encapsulant is added to Pezeshki’s device, then the package must further comprise:
an encapsulant (“mold”, see Para. 70; note exemplary mold 2268 in Fig. 5 of Ecton) covering the filling structure (117a and 117b of Pezeshki),
wherein an interface between the filling structure (117a and 117b) and the encapsulant (“mold”) comprises a curved surface (the encapsulant is interpreted as forming a curved surface at the apertures 122 of the interpreted filling structure 117a and 117b).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the encapsulant of Ecton in the device of Pezeshki for the purpose of providing a hermetic seal thereby achieving a device better protected against environmental factors.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki et al. in US 20220286211 A1 (hereinafter "Pezeshki") in view of Ecton et al. in US 20240176070 A1 (hereinafter "Ecton").
Regarding claim 12, Pezeshki discloses a semiconductor package (semiconductor package 117a; see Fig. 1A), comprising:
a first electronic element (optical transceiver chip 123a is interpreted as the first electronic element) disposed over a substrate (interposer 115a is interpreted as the substrate); and
a second electronic element (semiconductor chip 113a is interpreted as the second electronic element) disposed over the substrate (115a),
wherein the first electronic element (123a) is electrically connected (see Para. 30-33 which discusses electrical coupling between the semiconductor chip and the optical transceiver chip) to the second electronic element (113a) through the substrate (115a), and the first electronic element (123a) is non-electrically connected (see Para. 36 which discusses the optical signal transfer via multicore fiber 125) to an external element (optical transceiver chip 123b is interpreted as the external element) through an optical bump (direction changing coupling optics 126 is interpreted as the optical bump; see Fig. 1A) protruding from a surface of the first electronic element (123a).
Pezeshki suggests that the fiber may be connected to the underside of the electronic elements (as in Fig. 12), but fails to explicitly teach that the surface the optical bump protrudes from is facing the substrate.
Ecton that optical components (182) may be provided on the underside (see Fig. 1A) of electronic elements (PIC 104), such that they face a substrate (RDL 148-2). The examiner argues that Ecton’s arrangement may be used in the first module, such that:
the optical bump protruding from a surface of the first electronic element facing the first substrate (Ecton’s optical component 182 protrudes from the surface of PIC 104 facing layer 148-2)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the optical bump of Pezeshki protrude from the surface of the first electronic element facing the first substrate as taught by the arrangement of Ecton for the purpose of providing a better-protected attachment point during manufacturing thereby achieving a more reliable and durable optical connection and decreasing the overall rate of manufactured failures.
Regarding claim 13, Pezeshki/Ecton discloses the semiconductor package of claim 12 as discussed above. Pezeshki does not explicitly teach:
wherein the first electronic element has an overhang extending beyond an edge of the substrate, and the optical bump is disposed under the overhang.
Ecton teaches an arrangement with an overhang (see Fig. 1A) where the PIC 104 is interpreted as the electronic element and extends beyond the edge of the layer 148-2 which is interpreted as the substrate, and an optical element 182 is disposed under the overhang, thus Ecton teaches:
wherein the first electronic element has an overhang extending beyond an edge of the substrate, and the optical bump is disposed under the overhang (Ecton’s arrangement applied to the MCM module would result in the interpreted first electronic element 123ab having an overhang extending beyond the edge of the interpreted first substrate 115a and the interpreted optical bump is disposed under the overhang).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the overhang arrangement of Ecton in the package of Pezeshki for the purpose of providing a point of attachment on the underside of the electronic element thereby achieving a more reliable and durable optical connection and decreasing the overall rate of manufactured failures.
Regarding claim 14, Pezeshki/Ecton discloses the semiconductor package of claim 13 as discussed above, wherein the optical bump (126) is connected to the external element (123b) through an optical fiber (multicore optical fiber 125).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki et al. in US 20220286211 A1 (hereinafter "Pezeshki") as applied above, and in view of Matsui et al. in JP 2509274 B2 (hereinafter "Matsui") .
Regarding claim 27, Pezeshki discloses the semiconductor package of claim 15 as discussed above, but fails to teach that the first interconnection element comprises a negative photoresist material.
Matsui teaches a material that can be used as “a sheath material for optical fibers, a negative photoresist material, or the like” (see the first paragraph of the provided translation). Matsui further identifies that the material provides good heat resistance in the ninth paragraph.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the negative photoresist material of Matsui in the interconnection element (i.e., optical fiber) of Pezeshki for the purpose of providing good heat resistance thereby achieving cores less affected by thermal mismanagement, thus decreasing signal distortion, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
This prior art, made of record, but not relied upon, is considered pertinent to applicant’s disclosure since the following references have similar structure and/or use similar structure and/or similar optical elements to what is disclosed and/or claimed in the instant application:
US 11624882 B2 discloses a similar arrangement as applied above but with all optical interconnection.
US 10048439 B1 discloses a similar arrangement.
US 20090180732 A1 discloses an optical bump 41 in Fig. 3A.
US 7095620 B2 discloses optical connection on the underside of an electronic element.
US 20070223552 A1 discloses places an optical component between other components.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARBY M THOMASON whose telephone number is (703)756-5817. The examiner can normally be reached Mon.-Fri. 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARBY M. THOMASON/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874