DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 20, 2026 has been entered.
Response to Amendment
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 and 11-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Asad et al. (Asad”), US 2025/0374739 (the counterpart of PCT/US2022/048990, all citations in this rejection are directed to this PG Pub).
Regarding Claim 1, Asad discloses a display module (Fig. 21; ¶ 0062), comprising:
a substrate (103-1; Fig. 21; ¶ 0062), having a driving circuit (CMOS Driver; Fig. 21 in this instance the CMOS Driver within substrate 103-1; ¶ 0062);
an interposer (129-1, 129-2, 129-3, 129-7, 130-9, 132; Fig. 21; ¶ 0062), comprising an interlayer (132; Fig. 21; ¶ 0062), a testing circuit (129-7, 129-2, 129-3; Figs. 21, 22; ¶ 0063 “a probe head or probe card 158 that may be active or passive may make temporary electrical contact 129-7” so that “both electrical and optical characteristics of the micro-devices may be measured and validated”, therefore 129-7, 129-2, 129-3 facilitate testing) and an electrically conductive structure (129-1; Fig. 21; ¶ 0062-0063), wherein the testing circuit and the electrically conductive structure are located at the interlayer (Fig. 21), the testing circuit comprises a circuitry (129-2, 129-3; Figs. 21, 22; ¶ 0063) and a contact pad (129-7; Figs. 21, 22; ¶ 0063) electrically connected to each other (Figs. 21, 22; ¶ 0063), and the driving circuit is electrically connected with the electrically conductive structure (Fig. 21; ¶ 0062); and
a plurality of micro light emitting elements (101; Fig. 21; ¶ 0063 “micro-LEDs (micro-devices) 101”, therefore a plurality of micro light emitting elements), located at the interposer (Fig. 21), wherein the contact pad is electrically connected to the plurality of micro light emitting elements through the circuitry (Figs. 21-22, contact pad 129-7 is connected to the plurality of micro LEDs 101, through the circuitry 129-2/129-3).
Regarding Claim 2, Asad discloses wherein the substrate is a target substrate (Fig. 21; ¶ 0062 “CMOS driver may be capable of driving the micro-LEDs by modulation”) where the interposer and the plurality of micro light emitting elements are transferred (¶ 0062 note that this limitation is not given patentable weight because it is a process limitation in a product claim).
Regarding Claim 3, Asad discloses wherein the electrically conductive structure of the interposer extends through the interlayer (Fig. 21 specifically, 129-1 extends through 132).
Regarding Claim 4, Asad discloses wherein the plurality of micro light emitting elements are one-piece formed on the interlayer (Fig. 21 note that this limitation is not given patentable weight because it is a process limitation in a product claim, but one piece is formed on the interlayer for the structural element).
Regarding Claim 5, Asad discloses wherein the interlayer of the interposer has a first surface (Fig. 21 in this instance the bottom surface of 132) and a second surface (Fig. 21 in this instance the top surface of 132) opposite to each other (Fig. 21), the first surface faces toward the substrate (Fig. 21), and the testing circuit is located on the first surface (Fig. 21, 129-7 of the testing circuit is located on the first surface).
Regarding Claim 6, Asad discloses wherein the interlayer of the interposer has a first surface (Fig. 21 in this instance the bottom surface of 132) and a second surface (Fig. 21 in this instance the top surface of 132) opposite to each other (Fig. 21), the first surface faces toward the substrate (Fig. 21), and the testing circuit is located on the second surface (Fig. 21 in this instance 129-2, 129-3 of the testing circuit is located on the second surface).
Regarding Claim 7, Asad discloses further comprising an electrical connection element (rightmost 129-5; Fig. 12; ¶ 0053) between the substrate and the interlayer (Fig. 12 in this instance between substrate 130-5 and interlayer 132), wherein the driving circuit is electrically connected with the electrically conductive structure through the electrical connection element (Fig. 12).
Regarding Claim 8, Asad discloses wherein the electrical connection element comprises metal solder (¶ 0053 “solder pad 129-5”).
Regarding Claim 9, Asad discloses wherein a projection of each of the plurality of micro light emitting elements onto a surface of the substrate does not overlap a projection of the electrical connection element onto the surface (Fig. 14 in this instance a projection of 101,118 onto 130-5 does not overlap the rightmost electrical connection).
Regarding Claim 11, Asad discloses wherein the protective layer (Fig. 21 in this instance the unlabeled layer between 129-3 and 101, see the annotated Fi. 21 infra) and the testing circuit are located at opposite sides of the interlayer (Fig. 21 the protective layer and 129-7 of the testing circuit are located at opposite sides of the interlayer 132), respectively (Fig. 21).
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Regarding Claim 12, further comprising a buffer layer (130-2; Fig. 14; ¶ 0053) between the substrate and the interlayer of the interposer (Fig. 14; ¶ 0053 in this instance between substrate 130-5 and interlayer 132).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being anticipated by Asad et al. (Asad”), US 2025/0374739 (the counterpart of PCT/US2022/048990, all citations in this rejection are directed to this PG Pub), in view of Lin et al. (“Lin”), US 2021/0398865.
Asad does not specifically disclose furthering comprises a protective layer disposed on the interposer, wherein the protective layer covers the plurality of micro light emitting elements, and the protective layer and the interlayer together encapsulate the plurality of micro light emitting elements.
Lin discloses the display module (S; Figs. 1-6A; ¶ 0068) furthering comprises a protective layer (4; Figs. 1-6A; ¶ 0058 “4 is disposed on the multilayered circuit board 1”) disposed on (Fig. 5; ¶ 0058 “4 is disposed on the multilayered circuit board 1”) the interposer (1; Fig. 5; ¶ 0058 “multilayered circuit board 1”), wherein the protective layer covers the plurality of micro light emitting elements (Fig. 5; ¶ 0073 “4 surrounds the first, second, and third lighting elements 21, 22, 23”), and the protective layer (4; Fig. 5) and the interlayer (top layer IW of interposer 1; Figs. 4-6; ¶ 0058) together encapsulate the plurality of micro light emitting elements (Fig. 5; ¶ 0065 “lighting unit 2 can include…lighting elements 21, 22, 23”, ¶ 0058 “lighting unit 2 is disposed on the multilayered circuit board 1 and includes a plurality of lighting elements”, ¶ 0073 protective layer 4 is “disposed on the multilayered circuit board 1” and “surrounds the first, second, and third lighting elements 21, 22, 23”, therefore the protective layer and the interlayer together encapsulate the plurality of micro light emitting elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Asad to have furthering comprises a protective layer disposed on the interposer, wherein the protective layer covers the plurality of micro light emitting elements, and the protective layer and the interlayer together encapsulate the plurality of micro light emitting elements, as taught by Lin, because “4 has a reduced water absorption rate, thereby increasing the reliability of the LED package structure S” (Lin ¶ 0073).
Response to Arguments
The Applicant states (page 7 of 9) that “Asad fails to disclose the feature “the contact pad is electrically connected to the plurality of micro light emitting elements through the circuitry” of claim 1.”
As explained in the rejection of amended Claim 1 supra, Asad discloses wherein the contact pad is electrically connected to the plurality of micro light emitting elements through the circuitry (Figs. 21-22, contact pad 129-7 is connected to the plurality of micro LEDs 101, through the circuitry 129-2/129-3). In addition Asad discloses a plurality of micro light emitting elements (101; Fig. 21; ¶ 0063 “micro-LEDs (micro-devices) 101”, therefore a plurality of micro light emitting elements).
Independent Claim 1 is rejected for at least the reasons stated supra. Dependent Claims 2-12 are rejected for at least the reasons stated supra.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. The amended claim includes amended subject matter that was rejected using the same embodiment of the same art, Asad, used in the most recent rejection (final rejection with a mail date of February 19, 2026), therefore, would have been finally rejected on the grounds and art of record had the amendments been entered in the application prior to entry under 37 CFR 1.114. It is noted that Applicant removed the previously filed amendment from claim 1 and changed it to a dependent claim (claim 10). This dependent claim is rejected with the same combination as previously rejected, therefore, would have also been finally rejected on the grounds and art of record had the amendments been entered in the application prior to entry under 37 CFR 1.114
Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571) 270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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