Prosecution Insights
Last updated: August 17, 2026
Application No. 18/129,872

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT WIDENING

Non-Final OA §102§103
Filed
Apr 02, 2023
Examiner
TRAN, DZUNG
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
880 granted / 1054 resolved
+15.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
52 currently pending
Career history
1130
Total Applications
across all art units

Statute-Specific Performance

§101
5.2%
-34.8% vs TC avg
§103
66.1%
+26.1% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1054 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of the Claims Applicant’s election, without traverse, of Group I, claims 1-8, in the reply filed on June 15th, 2026, is acknowledged. Non-elected invention of Groups II and III, claims 9-20 have been withdrawn from consideration. Claims 1-20 are pending. Action on merits of Group I, claims 1-8 as follows. Information Disclosure Statement The information disclosure statement (IDS) submitted on August 14th, 2024 has been considered by the examiner. Drawings The drawings filed on 04/02/2023 are objected. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features: “a conductive source or drain contact vertically beneath and in contact with a bottom of the epitaxial source or drain structure, the conductive source or drain contact in a second cavity in the isolation layer” as recited in claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Xie (US 2023/0086033, hereinafter as Xie ‘033). Regarding Claim 1, Xie ‘033 teaches an integrated circuit structure, comprising: a plurality of horizontally stacked nanowires (Fig. 12A, (112); [0040]); a gate stack (Fig. 12A, (126); [0056]) over the plurality of horizontally stacked nanowires; an epitaxial source or drain structure (Fig. 12A, (122); [0053]) at an end of the plurality of horizontally stacked nanowires; and a conductive gate contact (Fig. 12A, (138); [0060]) vertically beneath and in contact with a bottom of the gate stack, the conductive gate contact in a cavity in an isolation layer (Fig. 12A, (136); [0060]), the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure (122), and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure (see Fig. 12A). PNG media_image1.png 466 324 media_image1.png Greyscale Fig. 12A (Xie ‘033) Regarding Claim 2, Xie ‘033 teaches the bottom of the gate stack (126) has a stepped feature (see Fig. 12D). Regarding Claim 3, Xie ‘033 teaches the cavity extends beyond two opposite edges of the gate stack in the direction parallel with the epitaxial source or drain structure (see Fig. 11D). Regarding Claim 4, Xie ‘033 teaches the cavity extends beyond only a single edge of the gate stack in the direction parallel with the epitaxial source or drain structure (see Fig. 12D). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Xie ‘033 as applied to claim 1 above, and further in view of Su (US 2022/0271138, hereinafter as Su ‘138). Regarding Claim 5, Xie ‘033 teaches a conductive source or drain contact (130; [0057]) vertically beneath and in contact with a bottom of the epitaxial source or drain structure (122). Thus, Xie ‘033 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the conductive source or drain contact in a second cavity in the isolation layer, the second cavity extending beyond the epitaxial source or drain structure in a direction parallel with the gate stack, and the second cavity confined to the epitaxial source or drain structure in a direction toward the gate stack”. Su ‘138 teaches the conductive source or drain contact (Fig. 15, (274); [0026]) in a second cavity in the isolation layer (Fig. 15, (278); [0027]), the second cavity extending beyond the epitaxial source or drain structure (Fig. 14, (230); [0016]) in a direction parallel with the gate stack (240; [0015]), and the second cavity confined to the epitaxial source or drain structure (230) in a direction toward the gate stack (240). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Xie ‘033 by having the conductive source or drain contact in a second cavity in the isolation layer, the second cavity extending beyond the epitaxial source or drain structure in a direction parallel with the gate stack, and the second cavity confined to the epitaxial source or drain structure in a direction toward the gate stack for the purpose of improving the semiconductor device performance (see para. [0011]) as suggested by Su ‘138. Regarding Claim 6, Su ‘138 teaches the second cavity extends beyond two opposite edges of the epitaxial source or drain structure (230) in the direction parallel with the gate stack (241) (see Figs. 14 and 15). Regarding Claim 7, Xie ‘033 teaches the cavity extends beyond only a single edge of the epitaxial source or drain structure (122) in the direction parallel with the gate stack (see Fig. 12B). Further, it has been held to be within the general skill of a worker in the art to select the cavity extends beyond only a single edge of the epitaxial source or drain structure on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the cavity extends beyond only a single edge of the epitaxial source or drain structure in order to improve the performance of the semiconductor device. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie ‘033 as applied to claim 1 above, and further in view of Glass (US 2020/0105871, hereinafter as Glass ‘871). Regarding Claim 8, Xie ‘033 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a second epitaxial source or drain structure at a second end of the plurality of horizontally stacked nanowires”. Glass ‘871 teaches a second epitaxial source or drain structure (Fig. 3, (310A/B); [0040]) at a second end of the plurality of horizontally stacked nanowires ((304A/B); [0038])). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Xie ‘033 by having a second epitaxial source or drain structure at a second end of the plurality of horizontally stacked nanowires in order to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance. (see para. [0043]) as suggested by Glass ‘871. Examiner’s Note Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices: Guha et al. (US 2021/0202696 A1) Glass et al. (US 2020/0357930 A1) Mannebach (US 2020/0219970 A1) Cheng et al. (US 10,516,064 B1) For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DZUNG TRAN/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 02, 2023
Application Filed
Aug 03, 2023
Response after Non-Final Action
Aug 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1054 resolved cases by this examiner. Grant probability derived from career allowance rate.

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