DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of invention Group I and Species IC (FIGs. 1C-1F), encompassing claims 1-5 and 11-20, in the reply filed on 6/15/2026 is acknowledged.
Claims 6-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/15/2026.
Claim Objections
Claim 20 is objected to because of the following informalities: Claim 20 ending with two periods “..” should be corrected to fix typographical error. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. US 2022/0319990 A1 (cited in IDS filed 9/6/2024; hereinafter, Huang).
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In re claim 1, Huang discloses (e.g. FIG. 2S) an integrated circuit structure (¶ 48), comprising:
alternating conductive lines 212 and air gaps 224 above a first dielectric layer 204;
a dielectric structure 222+226 between adjacent ones of the conductive lines 212 and over the air gaps 224;
a first etch stop layer 254 on the dielectric structure 222+226 but not on the conductive lines 212;
a second etch stop layer 232 on the first etch stop layer 254 and on the conductive lines 212;
a second dielectric layer 234 above the second etch stop layer 232; and
a conductive via structure 242+244 in the second dielectric layer 234, in the second etch stop layer 232, and on one of the conductive lines 212.
In re claim 2, Huang discloses (e.g. FIG. 2S) wherein the first etch stop layer 254 comprises aluminum and oxygen (¶ 61).
In re claim 3, Huang discloses (e.g. FIG. 2S) wherein the dielectric structure 222+226 comprises a liner portion 222 and a third dielectric layer 226 within the liner portion 222.
In re claim 4, Huang discloses (e.g. FIG. 2S) wherein the second etch stop layer 232 comprises silicon and nitrogen (232 has same material as 132 ¶ 63, which includes SiN ¶ 37).
In re claim 5, Huang discloses (e.g. FIG. 2S) wherein the conductive via structure 242+244 is further on a portion of the first etch stop layer 254.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 2022/0319990 A1 (cited in IDS filed 9/6/2024; hereinafter, Huang) in view of Hourani et al. US 2017/0330794 A1 (Hourani).
In re claim 11, Huang discloses (e.g. FIG. 2) a component including an integrated circuit structure(¶ 48), comprising:
alternating conductive lines 212 and air gaps 224 above a first dielectric layer 204;
a dielectric structure 222+226 between adjacent ones of the conductive lines 212 and over the air gaps 224;
a first etch stop layer 254 on the dielectric structure 222+226 but not on the conductive lines 212;
a second etch stop layer 232 on the first etch stop layer 254 and on the conductive lines 212;
a second dielectric layer 234 above the second etch stop layer 232; and
a conductive via structure 242+244 in the second dielectric layer 234, in the second etch stop layer 232, and on one of the conductive lines 212.
Huang discloses the interconnect structure 200 may be formed on various devices of a semiconductor structure (¶ 48).
Huang does not explicitly disclose the device component is embodied in a computing device, comprising: a board; and the component coupled to the board.
Hourani discloses an integrated circuit interconnection structure (FIG. 1) implemented in a computing device (FIG. 7) comprising a board 702 and a component 704 including the integrated circuit structure coupled to the board (¶ 51-54).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a circuit board for mounting Huang’s IC component to provide mounting support and electrical routings to implement a larger electrical system to perform the desired electrical functions as taught by Hourani.
In re claim 12, Huang discloses (e.g. FIG. 2S) wherein the first etch stop layer 254 comprises aluminum and oxygen (¶ 61).
In re claim 13, Huang discloses (e.g. FIG. 2S) wherein the dielectric structure 222+226 comprises a liner portion 222 and a third dielectric layer 226 within the liner portion 222.
In re claim 14, Hourani discloses (e.g. FIG. 7) further comprising: a memory (ROM, DRAM) coupled to the board 702 (¶ 51).
In re claim 15, Hourani discloses (e.g. FIG. 7) further comprising: a communication chip 706 coupled to the board 702 (¶ 51-52).
In re claim 16, Hourani discloses (e.g. FIG. 7) further comprising: a battery coupled to the board (¶ 51).
In re claim 17, Hourani discloses (e.g. FIG. 7) further comprising: a camera coupled to the board (¶ 51).
In re claim 18, Hourani discloses (e.g. FIG. 7) further comprising: a display coupled to the board (¶ 51).
In re claim 19, Huang discloses (e.g. FIG. 2S) wherein the component is a packaged integrated circuit die (¶ 1,48). No specific “packaged” structure has been claimed that would distinguish over the device taught by Huang. Hourani discloses (e.g. FIG. 7) wherein the component is a packaged integrated circuit die (¶ 53-54).
In re claim 20, Hourani discloses (e.g. FIG. 7) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (¶ 53-54).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights