Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Please see below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini (20200273840).
Regarding claim 1, Elsherbini teaches an electronic package (fig. 4), comprising:
a substrate (fig. 4: 102) with a first surface and a second surface opposite from the first surface;
a plurality of first dies (fig. 4: 114-2) coupled to the first surface of the substrate; and
a bump field (fig. 4: 150-2) on the second surface of the substrate, wherein the bump field comprises a
voided region towards a center of the substrate see region wherein 114-1 resides); and
a second die (fig. 114-1) coupled to the second surface of the substrate, wherein the second die is provided in the voided region such that the second die is in a same horizontal plane as the bump field (please see fig. 4).
Regarding claim 2, Elsherbini teaches an electronic package of claim 1, wherein the second die does not include transistors (par. 39).
Regarding claim 3, Elsherbini teaches an electronic package of claim 1, wherein at least one of the plurality of first dies is provided directly over the second die (see fig. 4 which shows this arrangement and par. 43).
Regarding claim 5, Elsherbini teaches an electronic package of claim 1, wherein the second die is coupled to the substrate
by an adhesive (as seen in fig. 4, 150-1 acts to adhere 114-1 to 102 ).
Regarding claim 6, Elsherbini teaches an electronic package of claim 1, wherein the second die is coupled to the substrate by interconnects (please see interconnects connected 102 to 114-1).
Regarding claim 7, Elsherbini teaches an electronic package of claim 6, wherein the second die is configured to supply power delivery and/or memory functionality to the electronic package (par. 37-45 and 65).
Regarding claim 8, Elsherbini teaches an electronic package of claim 1, wherein the substrate is a package substrate (par. 33).
Regarding claim 9, Elsherbini teaches an electronic package of claim 1, wherein the substrate is a board (par. 34).
Regarding claim 10, Elsherbini teaches an electronic package of claim 1, wherein an effective warpage of the substrate at room temperature is less than approximately 300µm (please see par. 34 for types of materials that fit this criteria).
Claims 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini (20200273840).
Regarding claim 11, Elsherbini teaches an electronic system, comprising:
a first substrate (fig. 22: 148);
a second substrate (fig. 153: 153) coupled to the first substrate by a plurality of interconnects (fig. 22: 134) between
the first substrate and the second substrate, wherein a voided region without interconnects is provided at a location towards a center of the second substrate (please area taken up by 114-1 in fig. 22);
a plurality of first dies (fig. 22: 114-2, 114-3,114-4) coupled to the second substrate on a surface opposite from the first substrate; and
a second die (fig. 22: 114-1) coupled to the first substrate, wherein the second die is positioned within the voided region such that the second die is in a same horizontal plane as the plurality of interconnects (please see fig. 22).
Regarding claim 12, Elsherbini teaches an electronic system of claim 11, wherein an effective warpage between the first substrate and the second substrate is approximately 200µm or less (par. 34 teaches that package substrate 148 and 153 can be comprised of materials satisfying this limitation).
Regarding claim 13, Elsherbini teaches an electronic system of claim 11, wherein the second die is coupled to the first substrate by an adhesive (150-1 acts to adhere 114-1 to 153).
Regarding claim 14, Elsherbini teaches an electronic system of claim 11, wherein the second die is coupled to the first substrate by interconnects (please see interconnects in 148 and 153 which uses 134 to connect electrically).
Regarding claim 15, Elsherbini teaches an electronic system of claim 11, wherein at least one of the plurality of first dies is provided directly over the second die (please see fig. 22 which shows this structural limitation).
Regarding claim 16, Elsherbini teaches an electronic system of claim 11, wherein the first substrate is a first board, and wherein the second substrate is a second board or a package substrate (par. 34).
Regarding claim 17, Elsherbini teaches an electronic system of claim 11, wherein the plurality of first dies comprises at least a compute die, a power management integrated circuit (PMIC), and a memory die (par. 37-45 and 65).
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini (20200273840).
Regarding claim 18, Elsherbini teaches an electronic system, comprising:
a first substrate (fig. 22: 148);
a second substrate (fig. 22: 153) coupled to the first substrate by interconnects (fig. 22: 134);
a first die (fig. 22: 144-2, 114-3, 114-4) coupled to the second substrate on a surface opposite from the first substrate;
and
a second die (fig. 22: 114-1) provided in a gap between the first substrate and the second substrate such that the second die is in a same horizontal plane as the interconnects, wherein the second die is provided under the first die (please see fig. 22).
Regarding claim 19, Elsherbini teaches an electronic system of claim 18, wherein the second die is coupled to the first substrate, or wherein the second die is coupled to the second substrate (please see fig. 22).
Regarding claim 20, Elsherbini teaches an electronic system of claim 19, wherein the electronic system is part of a personal
computer, a server, a mobile device, a tablet, or an automobile (par. 188).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4 an 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (20120126416).
Regarding claim 1, Lee teaches an electronic package, comprising:
a substrate (fig. 5: 140) with a first surface and a second surface opposite from the first surface;
a plurality of first dies (as seen in fig. 5, Lee teaches stacking chips atop one another, par. 53 teaches these chips being electrically connected) coupled to the first surface of the substrate; and
a bump field (fig. 5: 166) on the second surface of the substrate, wherein the bump field comprises a voided region towards a center of the substrate (please see area wherein 124 resides); and
a second die (fig. 5: 124) coupled to the second surface of the substrate, wherein the second die is provided in the voided region such that the second die is in a same horizontal plane as the bump field (please see fig. 5).
While only two dies are seen stacked in fig. 5, it would have been obvious to a PHOSITA at the time said invention was made to stack a third die 124 in order to increase circuit density while minimizing space used on the PCB. This motivation can further be found in Lee, par. 54, which teaches a skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention. Lastly, mere duplication of parts has no patentable significance unless a new and unexpected result is produced. The stacking of multiple chips would not present new and unexpected results.
Thus, it would have been obvious to a PHOSITA, at the time of filing, to utilize aforementioned teachings of the prior art(s) in the primary prior art(s) due to aforementioned reason(s).
Regarding claim 3, Lee teaches an electronic package of claim 1, wherein at least one of the plurality of first dies is provided directly over the second die (please see fig. 5).
Regarding claim 4, Lee teaches an electronic package of claim 3, wherein the at least one of the plurality of first dies over the second die has the same dimensions as the second die (stacked dies 124 are identical).
Regarding claim 9, Lee teaches an electronic package of claim 1, wherein the substrate is a board (fig. 1: 52).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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