CTNF 18/129,880 CTNF 91724 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. US PGPub. 2023/0397330 in view of Kuo et al. US PGPub. 2020/0075470. Regarding claim 1, Choi teaches an electronic package (100, fig. 3-4) [0032], comprising: a substrate (110/112, fig. 3-4) [0034] comprising a glass layer [0004]; a metallic layer (131+141, fig. 4) [0036] over the glass layer (112), the metallic (131+141) layer comprising one or more of palladium, titanium, and copper [0036] ; and a feature (132+142, fig. 4) [0036] over the metallic layer (131+141), wherein the feature (132+142) is electrically conductive (metal, [0036]) (Choi et al., fig. 3-4). But Choi fails to teach wherein sidewalls of the metallic layer (131+141) are sloped. However, Kuo teaches an electronic package (4, fig. 5 and 7) [0049] wherein sidewalls of the metallic layer (seed layer SLS, portion LL, fig. 7)[0097] are sloped (tapered, fig. 7, [0102]) (Kuo et al., fig. 7, [0102]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the metallic layer of Choi such that it has a sloped sidewall as taught by Kuo because such structure/shape of a metallic seed layer is well known in the art and such structure is art recognized and suitable for the intended purpose of using the seed layer as a footing layer which is beneficial to enhance the interface adhesion and reduce the metal from diffusing into the underlying device layers thereby stabilizing the impedance during reliability testing (Kuo et al., [0023]) (see MPEP 2144.07) . Regarding claim 5, Choi in view of Kuo teaches the electronic package of claim 1, wherein the feature (132+142) is a trace (wiring, [0033]) (Choi et al., [0033]). Regarding claim 6, Choi in view of Kuo teaches the electronic package of claim 1, wherein the feature (132+142) is a pad [0043] (Choi et al., [0043]). Regarding claim 7, Choi in view of Kuo teaches the electronic package of claim 1, wherein the metallic layer (131+141) is a seed layer [0037] (Choi et al., [0037]). Regarding claim 8, Choi in view of Kuo teaches the electronic package of claim 1, wherein the substrate (112/110) comprises a buildup layer (not shown, [0046]) over the glass layer (112), and wherein the metallic layer (131+141) is on the buildup layer (Choi et al., [0046]). Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Koo et al. US PGPub. 2022/0418107 in view of Kuo et al. US PGPub. 2020/0075470. Regarding claim 9, Koo teaches an electronic package (100, fig. 4) [0072], comprising: a core (110, fig. 4) [0075], wherein the core comprises glass [0075]; a via (140/141, fig. 4) [0070], [0089] through the core (110), wherein a first seed layer (120, fig. 4; hereinafter called 120-140) [0072] is provided between the via (141) and the core (110); and traces (130, fig. 4) [0072] over the core (110), wherein a second seed layer (120, fig. 4; hereinafter called 120-130) [0072] is provided between the traces (130) and the core (110) (Koo et al., fig. 4). But Koo fails to teach wherein sidewalls of the second seed layer (120-130) are sloped. However, Kuo teaches an electronic package (4, fig. 5 and 7) [0049] wherein sidewalls of a seed layer (seed layer SLS, portion LL, fig. 7)[0097] are sloped (tapered, fig. 7, [0102]) (Kuo et al., fig. 7, [0102]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the seed layer of Koo such that it has a sloped sidewall as taught by Kuo because such structure/shape of a metallic seed layer is well known in the art and such structure is art recognized and suitable for the intended purpose of using the seed layer as a footing layer which is beneficial to enhance the interface adhesion and reduce the metal from diffusing into the underlying device layers thereby stabilizing the impedance during reliability testing (Kuo et al., [0023]) (see MPEP 2144.07). Regarding claim 10, Koo in view of Kuo teaches the electronic package of claim 9, wherein the sidewalls (see LL fig. 7) of the second seed layer (SLS, LL) are sloped so that a bottom of the second seed layer (SLS/LL) is wider than a top of the second seed layer (SLS, LL) (Kuo et al., fig. 7). Regarding claim 11, Koo in view of Kuo teaches the electronic package of claim 9, wherein the via (140/141) is an hourglass shaped via [0122] (Koo et al., fig. 4, [0122]). Regarding claim 12, Koo in view of Kuo teaches the electronic package of claim 9, wherein the first seed layer (120-140) and the second seed layer (120-130) comprise one or more of palladium, titanium, and copper [0125] (Koo et al., [0125]). Regarding claim 13, Koo in view of Kuo teaches the electronic package of claim 9, further comprising: a buffer layer (one of the plurality of insulating layers of 110 above and below the center insulating layer, fig. 4; hereinafter called 110buff) [0074] over the core (center layer insulating layer of 110), wherein the via (140/141; PTH passes through all the plurality of insulating layers of 110, [0074]) passes through the buffer layer (110buff), and wherein the traces (130) are on the buffer layer (110buff) (Koo et al., fig. 4, [0074]). Regarding claim 14, Koo in view of Kuo teaches the electronic package of claim 13, wherein the via (141/140) has tapered sidewalls (see center portions of 141/140, fig. 4) (Koo et al., fig. 4) . 07-21-aia AIA Claim s 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rosch et al. US PGPub. 2019/0393143 in view of Kuo et al. US PGPub. 2020/0075470 . Regarding claim 17, Rosch teaches an electronic system (300, fig. 3) [0061], comprising: a board (302, fig. 3) [0061]; a package substrate (312, fig. 3) [0061] coupled (via bump 316, fig. 3) [0066] to the board (302), wherein the package substrate (details of portion 350 of 312, fig. 3 provided as 100, fig. 1A) [0062] comprises: a substrate (110, fig. 1A) [0029]; a seed layer (Cu seed on which 130-131 are formed [0030], not shown; hereinafter called 130-130’) over the substrate (110); and a feature (130, 131 fig. 1) over the seed layer (30-131’), wherein the feature (130, 131) is electrically conductive (Cu, [0025]); and a die (314, fig. 3) [0061] coupled (via bump 318, fig. 3) [0066] to the package substrate (312) (Rosch et al., fig. 1 and 3). But Rosch fails to teach wherein edges of the seed layer (130-131’) have a non-vertical profile. However, Kuo teaches an electronic system (4, fig. 5 and 7) [0049] wherein edges of a seed layer (seed layer SLS, portion LL, fig. 7)[0097] have a non-vertical profile (tapered, fig. 7, [0102]) (Kuo et al., fig. 7, [0102]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the seed layer of Rosch such that it has a sloped/non-vertical edge as taught by Kuo because such structure/shape of a metallic seed layer is well known in the art and such structure is art recognized and suitable for the intended purpose of using the seed layer as a footing layer which is beneficial to enhance the interface adhesion and reduce the metal from diffusing into the underlying device layers thereby stabilizing the impedance during reliability testing (Kuo et al., [0023]) (see MPEP 2144.07). Regarding claim 19, Rosch in view of Kuo teaches the electronic system of claim 17, wherein the non-vertical profile (LL, fig. 7) is an outward slope with a top surface that is narrower than a bottom surface (Kuo et al., fig. 7). Regarding claim 20, Rosch in view of Kuo teaches the electronic system of claim 17, wherein the electronic system (300) is part of a personal computer (700, fig. 7) [0121] , a server, a mobile device, a tablet, or an automobile (Rosch et al., fig. 7, [0121]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-4, 15-16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious an electronic package wherein “the feature is provided over a top surface of the metallic layer and over the sidewalls of the metallic layer ” as recited in claim 2 in combination with the rest of the limitations of claim 1; an electronic package wherein “the substrate adjacent to the sidewalls of the metallic layer is recessed” as recited in claim 3 in combination with the rest of the limitations of claim 1; an electronic package wherein “the buffer layer exhibits laser induced damage on a top surface” as recited in claim 15 in combination with the rest of the limitations of claims 9 and 13; and an electronic system wherein “the substrate adjacent to the edges of the seed layer is recessed by approximately 2 μm or more” as recited in claim 18 in combination with the rest of the limitations of claim 17. Claims 4 and 16 are also objected to as allowable for further limiting and depending upon allowable claims 3 and 15 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ko et al. US PGPub. 2023/0354520 teaches an electronic package (fig. 3) comprising a seed layer with a sloped sidewall/edge. Tuominen et al. US PGPub. 2021/0127496 teaches an electronic package comprising an hour glass shaped via through a core. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm .. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NDUKA E OJEH/Primary Examiner, Art Unit 2892 Application/Control Number: 18/129,880 Page 2 Art Unit: 2892 Application/Control Number: 18/129,880 Page 4 Art Unit: 2892 Application/Control Number: 18/129,880 Page 5 Art Unit: 2892 Application/Control Number: 18/129,880 Page 6 Art Unit: 2892 Application/Control Number: 18/129,880 Page 7 Art Unit: 2892 Application/Control Number: 18/129,880 Page 8 Art Unit: 2892 Application/Control Number: 18/129,880 Page 9 Art Unit: 2892
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