Office Action Predictor
Last updated: April 15, 2026
Application No. 18/130,070

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Apr 03, 2023
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
85%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
710 granted / 837 resolved
+16.8% vs TC avg
Minimal +1% lift
Without
With
+0.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
34.1%
-5.9% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 837 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (United States Patent Application Publication No. US 2021/0028281 A1, hereinafter “Kim”). In reference to claim 1, Kim discloses a device which meets the claim. Figures 4A and 4B of Kim disclose a semiconductor device which comprises an active region (R1, R2) extending in a first direction (Y-direction) on a substrate (10). There is a plurality of channel layers (120a-120c, 220a-220c) on the active region (R1, R2) and spaced apart from each other along a vertical direction (Z-direction) perpendicular to an upper surface of the substrate (10). A gate structure (130, 230) extends in a second direction (X-direction) crossing the active region (R1, R2) and the plurality of channel layers (120a-120c, 220a-220c) on the substrate (10) and encloses the plurality of channel layers (120a-120c, 220a-220c) respectively. A source/drain region (151-153, 251-253) is on the active region (R1, R2) on at least one side of the gate structure (130, 230) and contacts the plurality of channel layers (120a-120c, 220a-220c). The source/drain region (151-153, 251-253) comprises a first epitaxial layer (151, 251 – p. 3, paragraph 27) on the active region (R1, R2) and extends to contact the plurality of channel layers (120a-120c, 220a-220c) and a second epitaxial layer (152, 252). The first epitaxial layer (151, 251) extends between the plurality of channel layers (120a-120c, 220a-220c) and the second epitaxial layer (152, 252). At least a portion of a surface in which the first epitaxial layer (151, 251) and the second epitaxial layer (152, 252) are in contact with each other has first surfaces (horizontal surface in Y-direction) and second surfaces (vertical sloping direction) that face different directions. The gate structure (130, 230) comprises a lower gate portion (note unlabeled gate portion over (120a, 220a)), a middle gate portion (note unlabeled gate portion over (120b, 220b), on the lower gate portion (note unlabeled gate portion over (120a, 220a)), and an upper gate portion (note unlabeled gate portion over (120c, 220c)), on the middle gate portion (note unlabeled gate portion over (120b, 220b)), in a region overlapping the plurality of channel layers (120a-120c, 220a-220c) along the vertical direction (Z-direction). A lower end of the second epitaxial layer (152, 252) is disposed on a level substantially equal to or lower than a level of a lower surface of the lower gate portion (note unlabeled gate portion over (120a, 220a)) of the gate structure along the vertical direction (Z-direction). The first epitaxial layer (151, 251) comprises an upper portion on a level corresponding to a level of a center between an upper surface and a lower surface of the upper gate portion (note unlabeled gate portion over (120c, 220c)), a middle portion on a level corresponding to a level of a center between an upper surface and a lower surface of the middle gate portion (note unlabeled gate portion over (120b, 220b)), and a lower portion on a level corresponding to a level of a center between an upper surface and the lower surface of the lower gate portion (note unlabeled gate portion over (120a, 220a)). Each of the upper, middle, and lower portions of the first epitaxial layer (151, 251) has a horizontal length in the first direction (Y-direction) and a maximal horizontal length of the lower portion along the first direction (Y-direction) is greater than a maximal horizontal length of each of the upper portion and the middle portion along the first direction (Y-direction). With regard to claim 3, a lower end of the first epitaxial layer (151, 251) is disposed on a level lower than a level of the lower surface of the lower gate portion (note unlabeled gate portion over (120a, 220a)). In reference to claim 8, a third epitaxial layer (153, 253) is on the second epitaxial layer (152, 252). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cappellani et al. (United States Patent Application Publication No. US 2011/0147842 A1, hereinafter “Cappellani”). In reference to claim 2, Kim does not disclose that each of the second surfaces (vertical sloping direction) of the first (151, 251) and second (152, 252) epitaxial source/drain layers has a (111) crystal plane. However Cappellani discloses forming source/drain layers for a fin field effect transistor with surfaces having a (111) crystal plane (p. 4, paragraph 42). Cappellani also discloses that forming source/drain layers in this manner provides a wider surface area for a source/drain contact structure and a greater applied stress which leads to both a reduced source/drain resistance and a faster device (p. 1, paragraph 42) which are known goals in the art (p. 1, paragraphs 2-4). In view of Cappellani, it would therefore be obvious to implement first (151, 251) and second (152, 252) epitaxial source/drain layers that have second surface with a (111) crystal plane. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim. In reference to claim 5, Kim does not disclose the exact horizontal length of the lower portion as that claimed by the applicant. Although Kim does not teach the exact length as that claimed by the applicant: Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Size and dimension differences are generally not sufficient to patentably distinguish from the prior art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). In view of the above, adjusting the horizontal length of the lower portion to optimal values is considered to be obvious to one with ordinary skill in the art. Therefore this limitation is not patentable over Kim. In reference to claim 6, Kim does not disclose the exact horizontal lengths of the upper and middle portions as that claimed by the applicant. Although Kim does not teach the exact lengths as that claimed by the applicant: Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Size and dimension differences are generally not sufficient to patentably distinguish from the prior art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). In view of the above, adjusting the exact horizontal lengths of the upper and middle portions to optimal values is considered to be obvious to one with ordinary skill in the art. Therefore this limitation is not patentable over Kim. Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. (United States Patent Application Publication No. US 2016/0087104 A1, hereinafter “Lee”) and further in view of Ting et al. (United States Patent Application Publication No. US 2020/0105876 A1, hereinafter “Ting”). In reference to claim 9, Kim does not disclose that the first (151, 251), second (152, 252), and third (153, 253) epitaxial source/drain layers are formed of silicon germanium with respective first, second, and third germanium concentrations such that the third concentration is greater than the second concentration and the second concentration is greater than the first concentration. However figure 8 of Lee discloses the use of first (E1), second (E2), and third (E3) epitaxial source/drain layers that are formed of silicon germanium. Lee discloses that this is done to provide stress to the fins of the fin field effect transistor (p. 4, paragraph 68). Ting discloses that applying stress to the fins/channels of the fin field effect transistor increases their performance speed which is desirable in the art (p. 6, paragraph 70). In view of Lee and Ting, it would therefore be obvious to implement first, second, and third epitaxial source/drain layers that are formed of silicon germanium in the Kim device. In the device of Kim constructed in view of Lee and Ting, Lee discloses (p. 8, paragraphs 93-95) that the first (E1), second (E2), and third (E3) epitaxial source/drain layers have germanium concentrations such that the first epitaxial layer (E1) has a first germanium concentration (30 at%) that is lower than a second germanium concentration (between 30 at% and 70 at%) of the second epitaxial layer (E2). Lee discloses that the second germanium concentration of the second epitaxial layer (E2) and the third germanium concentration of the third epitaxial layer (32) are both between 30 at% and 70 at%. Lee does not explicitly disclose that the second germanium concentration of the second epitaxial layer (E2) is lower than the third germanium concentration of the third epitaxial layer (E3). However Ting discloses that increasing the germanium concentration of the source/drain regions also increases the stress applied to the fins/channels of the fin field effect transistor (p. 6, paragraph 70. Thus Ting makes it clear that the germanium concentration is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the germanium concentrations of the second and third source/drain epitaxial layers such that the second germanium concentration of the second epitaxial layer (E2) is lower than the third germanium concentration of the third epitaxial layer (E3) in order to tailor the stress and ultimately the device speed, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 9 is not patentable over Kim, Lee, and Ting. With regard to claim 10, the source/drain region (151-153, 251-253) further comprises a capping layer (155, 255) disposed on the third epitaxial layer (153, 253). In reference to claim 11, an interlayer insulating layer (90) is on the source/drain region (151-153, 251-253). Although not explicitly shown in fig. 4A and 4B, it is understood that a contact plug is implemented which passes through at least a portion of the interlayer insulating layer (90) and contacts the source/drain region (151-153, 251-253) in order for the fin field effect transistor to electrically communicate with the rest of the circuit. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee and further in view of Ting as applied to claim 11 above and further in view of Choi et al. (United States Patent Application Publication No. US 2018/0090583 A1, hereinafter “Choi”). In reference to claim 12, Kim does not disclose that the contact plug comprises a metal-semiconductor compound layer with a lower end of the metal-semiconductor compound layer being located on a level lower than an upper end of the plurality of channel layers. However figure 2A of Choi discloses a contact plug (145) that comprises a metal-semiconductor compound layer (a silicide – p. 3, paragraphs 39-40) with the lower end of the metal-semiconductor compound layer (145) being located on a level lower than an upper end of the channel layer (FA). Choi discloses (p. 3, paragraphs 39-40) that such a structure leads to a large contact area and thus a reduced contact resistance which is a known goal in the art (p. 1, paragraph 4). In view of Choi, it would therefore be obvious to implement a contact plug with a metal-semiconductor compound layer that has a lower end being located on a level lower than an upper end of the channel layer. In the device of Kim constructed in view of Lee, Ting, and Choi, the lower end of the metal-semiconductor compound layer is located on a level lower than an upper end of the plurality of channel layers (120a-120c, 220a-220c – fig. 4A and 4B of Kim). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cappellani. In reference to claim 20, Kim discloses a similar device. Figures 4A and 4B of Kim disclose a semiconductor device which comprises an active region (R1, R2) extending in a first direction (Y-direction) on a substrate (10). There is a plurality of channel layers (120a-120c, 220a-220c) on the active region (R1, R2) and spaced apart from each other along a vertical direction (Z-direction) perpendicular to an upper surface of the substrate (10). A gate structure (130, 230) extends in a second direction (X-direction), crosses the active region (R1, R2) and the plurality of channel layers (120a-120c, 220a-220c) on the substrate (10), and encloses the plurality of channel layers (120a-120c, 220a-220c) respectively. A source/drain region (151-153, 251-253) is on the active region (R1, R2) on at least one side of the gate structure (130, 230) and contacts the plurality of channel layers (120a-120c, 220a-220c). The gate structure (130, 230) comprises a plurality of gate portions (note three unlabeled gate portions over (120a, 220a, 120b, 220b, 120c, 220c)) that overlap the plurality of channel layers (120a-120c, 220a-220c) along the vertical direction (Z-direction) and spaced apart from each other along the vertical direction (Z-direction). The source/drain region (151-153, 251-253) comprises a first epitaxial layer (151, 251 – p. 3, paragraph 27) on the active region (R1, R2) and extends to contact the plurality of channel layers (120a-120c, 220a-220c) and a second epitaxial layer (152, 252). The first epitaxial layer (151, 251) extends between the plurality of channel layers (120a-120c, 220a-220c) and the second epitaxial layer (152, 252). The first epitaxial layer (151, 251) comprises epitaxial portions that correspond to the plurality of gate portions (note three unlabeled gate portions over (120a, 220a, 120b, 220b, 120c, 220c)). Along the first direction (Y-direction), a widest epitaxial portion (151, 251) among the epitaxial portions is a lowermost epitaxial portion (note region laterally adjacent to channel region (120a, 220a)). Kim does not disclose that at least a portion of a surface in which the first (151, 251) and second (152, 252) epitaxial source/drain layers are in contact with each other has a (111) crystal plane. However Cappellani discloses forming source/drain layers for a fin field effect transistor with surfaces having a (111) crystal plane (p. 4, paragraph 42). Cappellani discloses that forming source/drain layers in this manner provides a wider surface area for a source/drain contact structure and a greater applied stress which leads to both a reduced source/drain resistance and a faster device (p. 1, paragraph 42) which are known goals in the art (p. 1, paragraphs 2-4). In view of Cappellani, it would therefore be obvious to implement at least a portion of a surface in which the first (151, 251) and second (152, 252) epitaxial source/drain layers are in contact with each other has a (111) crystal plane. Kim does not disclose the exact maximum width of the lowermost epitaxial portion (note region laterally adjacent to channel region (120a, 220a)) as that claimed by the applicant. Although Kim does not teach the exact width as that claimed by the applicant: Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Size and dimension differences are generally not sufficient to patentably distinguish from the prior art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). In view of the above, adjusting the maximum width of the lowermost epitaxial portion to optimal values is considered to be obvious to one with ordinary skill in the art. Therefore this limitation is not patentable over Kim and Cappellani. Allowable Subject Matter Claims 13-19 are allowed. Claims 4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device with a plurality of channel layers on an active region (which extends in a first direction) which is crossed and enclosed by a gate structure (which extends in a second direction), a source/drain region on the active region and on at least one side of the gate structure and also contacts the plurality of channel layers in combination with the explicit structure of the first and second epitaxial layers as explicitly described by the applicant in claim 13. In the examiner’s opinion, it would also not be obvious to implement a semiconductor device with a plurality of channel layers on an active region (which extends in a first direction) which is crossed and enclosed by a gate structure (which extends in a second direction) with upper, middle, and lower portions, a source/drain region on the active region and on at least one side of the gate structure and also contacts the plurality of channel layers in combination with the location of the first and second epitaxial layers on the upper, middle, and lower portions of the gate structure and the explicit structure of the first and second epitaxial layers and the horizontal length differences between the portions of the first epitaxial layer as required by the applicant in claim 4 and 7. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Apr 03, 2023
Application Filed
Dec 13, 2025
Non-Final Rejection — §102, §103
Feb 25, 2026
Interview Requested
Mar 03, 2026
Applicant Interview (Telephonic)
Mar 04, 2026
Examiner Interview Summary
Apr 02, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
85%
With Interview (+0.6%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 837 resolved cases by this examiner. Grant probability derived from career allow rate.

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