DETAILED ACTION
This Office action is in response to the application filed 4 April 2023. Claims 1-29 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-29 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0013386 A1 to Shinohara et al. (hereinafter “Shinohara”) in view of US 2020/0373419 A1 to Cui et al. (hereinafter “Cui”).
Regarding claim 1, Shinohara (Figs. 2a-2c) discloses a field-effect transistor (FET), comprising: a substrate 30 (Fig. 2a, ¶ 0018); an epitaxial channel layer 34 (Fig. 2b, ¶ 0018) on said substrate; source and drain electrodes 38/40 (Fig. 2b; ¶ 0018); and a gate electrode, comprising: a plurality of buried gate structures 42 (¶ 0018), the tops of which extend above said substrate's top surface (Fig. 2a) and the bottoms of which are buried to a depth at least equal to that of the bottom of the current-carrying portion of said epitaxial channel layer 34 (Fig. 2b), such that said buried gate structures 42 contact said epitaxial channel layer 34 only from the sides of said epitaxial channel layer 34 (¶ 0018); wherein said epitaxial channel layer 34 comprises multiple channel segments (Fig. 2c - segments separated by buried gate structures 42), each of said channel segments having a width Wch (¶ 0019) defined as the distance between adjacent ones of said buried gate structures (Fig. 2c); and a head portion 44 (Fig. 2a; ¶ 0018) above and not in contact with said substrate's top surface 30 which contacts and interconnects all of said buried gate structures 42 (Fig. 2a); such that said FET's drain current is controlled by channel width modulation by lateral gating of the channel layers by said buried gate structures (¶ 0018).
Shinohara discloses varying channel segment widths by varying buried gate structure pitch for the express purpose of providing desired transfer characteristics for the FET (¶¶ 0025-26), however does not expressly disclose: each of said channel segment widths varying along the depth direction. In the same field of endeavor, Cui (Fig. 6) discloses a FET including channel segment widths (Fig. 6 - note tapered shape of channel regions 28, width increasing along a depth direction) varying along a depth direction (¶ 0038). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the FET of Shinohara to include channel segment widths varying along the depth direction as disclosed by Cui for the purpose of uniform current distribution and improved thermal dissipation (¶ 0038).
Regarding claim 2, Shinohara and Cui disclose the FET of claim 1, wherein each of said multiple channel segments has associated sidewalls (Cui, Fig. 6 - sidewalls of 28). The limitations “the slope of said sidewalls controlled to provide a desired transfer characteristic for said FET” are considered claimed properties or functions. Shinohara and Cui disclose the structure as recited in the claim as currently drafted, thus the structure of Shinohara and Cui inherently possesses the recited properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 3, Shinohara and Cui disclose the FET of claim 2, the remaining limitations “said FET having an associated transconductance (gm), the slope of said sidewalls controlled to minimize gm″ and the slope of the gm″−Vgs curve near the point at which gm″=0” are considered claimed properties or functions. Shinohara and Cui disclose the structure as recited in the claim as currently drafted, thus the structure of Shinohara and Cui inherently possesses the recited properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 4, Shinohara and Cui disclose the FET of claim 2, however fail to expressly disclose wherein said multiple channel segments are arranged such that their widths become narrower with depth. Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975). Here, the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to the claimed widths becoming narrower with depth (as compared with widths becoming wider with depth, as in claim 5), thus for this reason and in view of the disclosures of Shinohara and Cui, the recited particular arrangement is deemed to have been a design consideration within the skill of the art.
Regarding claim 5, Shinohara and Cui disclose the FET of claim 2, wherein said multiple channel segments 28 are arranged such that their widths become wider with depth (Cui, Fig. 6).
Regarding claim 6, Shinohara and Cui disclose the FET of claim 1, wherein said current-carrying portion of said epitaxial channel layer 34 comprises a two-dimensional electron gas (2DEG) plane (Shinohara, Fig. 2b, ¶ 0018).
Regarding claim 7, Shinohara and Cui disclose the FET of claim 6, and in a different embodiment, Shinohara discloses: wherein said epitaxial channel layer comprises multiple epitaxial channel layers 170/172/174/176 (Shinohara Fig. 7c, ¶ 0047) stacked in the depth direction, each of which comprises a 2DEG plane (¶ 0047). Shinohara contemplates variations and rearrangements of disclosed embodiments (¶ 0048), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine features of disclosed embodiments to include multiple epitaxial channel layers for the purpose of forming a FET with improved reliability and high frequency performance (¶ 0006).
Regarding claim 8, Shinohara and Cui disclose the FET of claim 7, Shinohara discloses wherein said FET's top surface comprises GaN (¶ 0033) and each of said multiple epitaxial channel layers comprises an AlGaN barrier and a GaN channel (¶ 0035).
Regarding claim 9, Shinohara and Cui disclose the FET of claim 7, the limitations “wherein the threshold voltage of each of said channel segments varies along the depth direction” are considered claimed properties or functions. Shinohara and Cui disclose the structure as recited in the claim as currently drafted, thus the structure of Shinohara and Cui inherently possesses the recited properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 10, Shinohara and Cui disclose the FET of claim 9, the limitations “wherein said varied threshold voltages provide multiple transfer curves for said FET which are superposed to provide said FET's overall transfer characteristic” are considered claimed properties or functions. Shinohara and Cui disclose the structure as recited in the claim as currently drafted, thus the structure of Shinohara and Cui inherently possesses the recited properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 11, Shinohara and Cui disclose the FET of claim 1, and in a different embodiment, Shinohara discloses wherein said epitaxial channel layer is uniformly doped (¶¶ 0039-43). Shinohara contemplates variations and rearrangements of disclosed embodiments (¶ 0048), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine features of disclosed embodiments to include a uniformly doped epitaxial channel layer for the purpose of forming a different type of FET (MESFET) with improved reliability and breakdown voltage (¶¶ 0006-08).
Regarding claim 12, Shinohara and Cui disclose the FET of claim 1, wherein said FET is a high electron mobility transistor (HEMT) (Shinohara, ¶ 0018).
Regarding claim 13, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures are cylindrical (Shinohara, ¶ 0023).
Regarding claim 14, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures are rectangular (Shinohara, ¶ 0023).
Regarding claim 15, Shinohara and Cui disclose the FET of claim 1, wherein said plurality of buried gate structures lie along a line which is parallel to and between said source and drain electrodes (Shinohara, Fig. 2a).
Regarding claim 16, Shinohara and Cui disclose the FET of claim 15, wherein said plurality of buried gate structures are evenly spaced along said line (Shinohara, Fig. 2a).
Regarding claim 17, Shinohara (Fig. 2a) and Cui disclose the FET of claim 15, in a different embodiment, Shinohara discloses wherein said plurality of buried gate structures are not evenly spaced along said line (Fig. 3). Shinohara contemplates variations and rearrangements of disclosed embodiments (¶ 0048), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine features of the disclosed embodiments to include unevenly spaced buried gate structures in the embodiment of Fig. 2a for the purpose of varying the pitch between buried gate structures to provide desired transfer characteristics for the FET (¶ 0026).
Regarding claim 18, Shinohara and Cui disclose the FET of claim 1, in a different embodiment, Shinohara discloses wherein said FET is a metal-semiconductor field-effect transistor (MESFET), comprising: an epitaxial buffer layer on said substrate; and said epitaxial channel layer on said buffer layer (Shinohara, ¶ 0039). Shinohara contemplates variations and rearrangements of disclosed embodiments (¶ 0048), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine features of disclosed embodiments to include a MESFET comprising an epitaxial buffer layer configured as recited for the purpose of forming a different type of FET (MESFET) with improved reliability and breakdown voltage (¶¶ 0006-08).
Regarding claim 19, Shinohara and Cui disclose the FET of claim 18, wherein said epitaxial buffer layer comprises GaN, and said epitaxial channel layer comprises n-type or p-type GaN on said buffer layer (Shinohara, ¶¶ 0039-40).
Regarding claim 20, Shinohara and Cui disclose the FET of claim 18, wherein said epitaxial channel layer comprises n-type or p-type GaN, Al(Ga)N, (In)GaAs, InP, or Ga.sub.2O.sub.3 (Shinohara, ¶¶ 0039-40).
Regarding claim 21, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures comprise metals, or p-type semiconductors (p-type NiO material, p-type GaN material, p-type CuS material, or a stack comprising a gate dielectric and a metal) (Shinohara, ¶ 0033).
Regarding claim 22, Shinohara and Cui disclose the FET of claim 21, wherein said metals comprise Pt, Ni, or Au (Shinohara, ¶ 0033).
Regarding claim 23, Shinohara and Cui disclose the FET of claim 21, wherein said stack comprises Al.sub.2O.sub.3/Pt or HfO.sub.2/Pt (Shinohara, ¶ 0033).
Regarding claim 24, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures comprise p-type NiO material (Shinohara, ¶ 0033).
Regarding claim 25, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures comprise p-type GaN material (Shinohara, ¶ 0033).
Regarding claim 26, Shinohara and Cui disclose the FET of claim 1, wherein said buried gate structures comprise p-type CuS material (Shinohara, ¶ 0033).
Regarding claim 27, Shinohara and Cui disclose the FET of claim 1, in a different embodiment Shinohara discloses further comprising a dielectric material 84 between said substrate's top surface and said head portion 80 (Fig. 4b; ¶ 0028). Shinohara contemplates variations and rearrangements of disclosed embodiments (¶ 0048), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine features of the disclosed embodiments to include a dielectric material between said substrate’s top surface and said head portion in the embodiment of Fig. 2a for the purpose of preventing modulation of the FET current and thus improving device performance (Shinohara, ¶ 0028).
Regarding claim 28, Shinohara and Cui disclose the FET of claim 27, wherein said dielectric material comprises SiN, SiO.sub.2, BCB, or air (Shinohara, ¶ 0028).
Regarding claim 29, Shinohara and Cui disclose the FET of claim 1, wherein said epitaxial channel layer comprises: Al.sub.xGa.sub.1-xN/Al.sub.yGa.sub.1-yN (x>y), AlGaAs/(In)GaAs, InAlAs/InGaAs, or (Al.sub.xGa.sub.1-x).sub.2O.sub.3/Ga.sub.2O.sub.3 (Shinohara, ¶¶ 0034-38).
Conclusion
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CANDICE Y. CHAN
Examiner
Art Unit 2813
23 September 2025
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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