DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7,9,13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US Pub No. 20200020725), in view of Chen et al (US Pub No. 20180166475).
With respect to claim 7, Tsai et al discloses an image sensor (Fig.3) including a semiconductor substrate (210) having a first surface (next to 230) and a second surface that is opposite the first surface (next to 214), the image sensor comprising: a pixel array (Fig.3) having a plurality of pixels (220) disposed on the semiconductor substrate (Fig.3);a plurality of trenches in the semiconductor substrate arranged within the pixel array separating adjacent pixels (270,290), each of the plurality of trenches extending from the first surface (Fig.3) into the semiconductor substrate forming a first opening proximate to the first surface (Fig.3) and a second opening proximate to the second surface (Fig.3); and a first material layer (284) disposed on the second surface (Fig.3), the first material layer continuously lining the second surface (Fig.3) and extending through the second opening to line(Fig.3) a plurality of sidewall surfaces of the plurality of trenches (Fig.3). However, Tsai et al does not explicitly disclose wherein the first opening has a width greater than that of the second opening. On the other hand, Chen et al discloses wherein the first opening (103 surface 130, FIg.3H) has a width greater than that of the second opening (near 102b). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Tsai et al according to the teachings of the Chen et al such that the first opening has a width greater than that of the second opening, in order to etch the trench from the first surface; thereby increasing the process speed by maximizing the process on the first surface.
With respect to claim 9, Tsai et al in view of Chen et al discloses wherein the plurality of sidewall surfaces are formed from the first surface of the semiconductor substrate (Chen et al Fig.3A-3C) and a distance that each of the plurality of trenches extends into the semiconductor substrate is equal to a substrate thickness of the semiconductor substrate (Tsai et al, Fig.3).
With respect to claim 13, Tsai et al discloses wherein the first material layer (214) is in contact with a dielectric layer (230, para 15) disposed on the first surface (Fig.3).
With respect to claim 14, Tsai et al discloses further comprising a circuit layer that includes a multi- layer interconnection structure embedded in the dielectric layer (230,para 15) .
Claim(s) 8,10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US Pub No. 20200020725), in view of Chen et al (US Pub No. 20180166475), in view of Chaing et al (US Pub No. 20170133414).
With respect to claim 8, the arts cited above do not explicitly disclose wherein the first material layer is a high-K dielectric material layer. On the other hand, Chiang et al discloses wherein the first material layer is a high-K dielectric material layer (107,Fig.10, para 20). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the Chiang et al such that the first material is made from high dielectric layer in order to decrease the cross talk between pixels; therefore, improving the picture quality.
With respect to claim 10, Chen et al discloses wherein each of the trenches having a width (Fig.1I) decreasing with an increasing distance from the first surface toward the second surface (Fig.1I); however, the arts cited above do not explicitly disclose wherein the plurality of trenches is interconnected forming a trench grid separating the plurality of pixels. On the other hand, Chiang et al discloses wherein the plurality of trenches (108,110,Fig.1) is interconnected forming a trench grid (Fig.1) separating the plurality of pixels (104). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Chiang et al such that isolation trenches make a grid structure to completely isolate the pixels from one another to decrease crosstalk between the pixels.
With respect to claim 11, the arts cited above do not explicitly disclose further comprising a second material layer disposed on the first material layer, the second material layer continuously lining the second surface and the plurality of sidewall surfaces of the plurality of trenches. On the other hand, Chiang et al discloses a second material layer (109) disposed on the first material layer (107), the second material layer continuously lining the second surface and the plurality of sidewall surfaces of the plurality of trenches(Fig.11). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings Chiang et al such that a second material layer disposed on the first material layer, the second material layer continuously lining the second surface and the plurality of sidewall surfaces of the plurality of trenches, in order to decrease diffusion of the trench material into the substrate; therefore, decreasing device defect.
With respect to claim 12, Chiang et al discloses the second material layer having a different material composition than that of the first material layer (Para 20).
Response to Arguments
Applicant's arguments filed on 07/09/2026 have been fully considered but they are not persuasive. Reference Chen et al is used to show the size of the first opening, maybe greater than the second opening. Liners106, passivation material 150 are immaterial here. Applicant is stating that this modification require substantial reengineering of the trench. All this modification would do is start forming the trench from the front of the substrate instead of the back of the substrate. These two references are from the same field of the invention, and the motivations are from themselves.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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