Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation in claim 14 of “a pitch of the upper and lower gate electrodes being different” must be shown or the feature(s) canceled from the claim(s). As drawings do not show a pitch of the upper and lower gate electrodes being different, the drawings appear to show the same pitch. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
In response to the applicants’ arguments filed on 06/10/2026, the 112(b) rejection has been rescinded as the indefinite language has been amended to be definite. Regarding the objected drawings, the objection is maintained as the pitch of the top electrode is merely shifted by the distance of the gate cut [gate electrode changes size so the center changes, the center of the top gate electrode is not in the same spot as the center of the bottom gate electrode], thus the pitch is no longer different but still the same but shifted. Note that a pitch is defined as a “center to center” distance, if the gate electrode decreases in size in one direction the center of the gate electrode shifts and is changed, if both gate electrodes shift the same amount in the same direction, mathematically the pitch doesn’t change it merely shifts the centers of the electrodes in the particular direction of the shift.
Regarding applicants arguments regarding independent claim 1, the applicants amendments overcome the previous prior art rejection, however a new rejection is formulated with a new base reference. The arguments pertaining to Lee et al no longer apply to the current rejection.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 9-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al (US 10833078).
Smith et al teaches
[claim 1] A semiconductor device, comprising: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second direction different from the first direction (figure 4, col 10 lines 7-44, where elements 25 and 23 comprise the fist active pattern and it extends into the page [called z-direction], which is the first direction. Elements 22 and 24 is the second active pattern and extends in the first direction [into the page], and is spaced apart from the first active pattern in a second direction [x-direction], which is different than the first direction);
a first bottom gate electrode extended in the second direction on the first active pattern (figure 17, col 21 line 49 – col 22 line 4, where element 33 is the first gate electrode and is situated over the first active region [element 23], and extends in a second direction [x-direction]);
a first upper gate electrode extended in the second direction on the first bottom gate electrode, the first upper gate electrode being spaced apart from the first bottom gate electrode in a third direction (figure 17, col 21 line 49 – col 22 line 4, where element 35 is the first upper gate electrode and extends in a second direction [x-direction] and the first gate electrode [element 35] is separated from the first bottom gate electrode [element 33] by a third direction [y-direction]),
a second bottom gate electrode extended in the second direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second direction (figure 17, col 21 line 49 – col 22 line 4, where element 32 is the second bottom gate electrode and extends in a second direction [x-direction] and spaced apart from the first bottom gate electrode [element 33] in a second direction [x-direction]);
a second upper gate electrode extended in the second direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the third direction, the second upper gate electrode being spaced apart from the first upper gate electrode in the second direction (figure 17, col 21 line 49 – col 22 line 7, where element 34 is the second upper gate electrode and extends in a second direction [x-direction] and spaced apart from the second bottom gate electrode [element 32] in a third direction [y-direction], and spaced apart from the first upper gate electrode [element 35] in a second direction [x-direction]),
and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode, wherein the first gate cut comprises isolation materials (figure 18, col 24 lines 8-39, where element 1410 is the gate cut, the first gate cut comprising element 1410, where the first portion is the portion surrounds the first and second bottom gate electrodes [elements 33 and 32], and the second portion is the portion that surrounds the first and second upper gate electrodes [elements 35 and 34], and comprise isolation materials),
wherein a width in the second direction of the second portion of the first gate cut exceeds a width in the second direction of the first portion of the first gate cut, and wherein the second portion of the first gate cut overlaps at least one of the first bottom gate electrode and the second bottom gate electrode in the third direction (figure 18, col 24 lines 8-39, where the second portion [as shown in figure 1 below] which surrounds the first and second upper gate electrodes [elements 34 and 35] extends in a second direction [x-direction] with a width that is greater than the width of the first portion [the portion of 1410 that surrounds the first and second bottom gate electrodes, 32 and 33], and element 1410 in the second portion [portion surrounding elements 34 and 35] overlaps a first and second bottom gate electrode [33 and 32] in the third direction [y-direction]).
[claim 2] The semiconductor device of claim 1, further comprising: a plurality of first bottom nanosheets stacked in the third direction on the first active pattern, the plurality of first bottom nanosheets being spaced apart from each other in the third direction, the plurality of first bottom nanosheets being surrounded by the first bottom gate electrode (figure 4, col 12, lines 38-49, where element 23 is the first bottom nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the first active patter [element 23 pattern], where it is surrounded by the first lower gate electrode [element 33]);
a plurality of first upper nanosheets stacked in the third direction on the plurality of first bottom nanosheets, the plurality of first upper nanosheets being spaced apart from each other in the third direction, the plurality of first upper nanosheets being surrounded by the first upper gate electrode (figure 4, col 12, lines 38-49, where element 25 is the first upper nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the first active patter [element 25 pattern], where it is surrounded by the first upper gate electrode [element 35]);
a plurality of second bottom nanosheets stacked in the third direction on the second active pattern, the plurality of second bottom nanosheets being spaced apart from each other in the third direction, the plurality of second bottom nanosheets being surrounded by the second bottom gate electrode (figure 4, col 12, lines 38-49, where element 222 is the second bottom nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the second active patter [element 22 pattern], where it is surrounded by the second lower gate electrode [element 32]);
and a plurality of second upper nanosheets stacked in the third direction on the plurality of second bottom nanosheets, the plurality of second upper nanosheets being spaced apart from each other in the third direction, the plurality of second upper nanosheets being surrounded by the second upper gate electrode (figure 4, col 12, lines 38-49, where element 24 is the second upper nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the second active patter [element 24 pattern], where it is surrounded by the second upper gate electrode [element 34]);
[claim 3] The semiconductor device, further comprising: a first isolation layer disposed between the plurality of first bottom nanosheets and the plurality of first upper nanosheets (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 situated directly between elements 25 and 23);
and a second isolation layer disposed between the plurality of second bottom nanosheets and the plurality of second upper nanosheets (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 situated directly between elements 24 and 22).
[claim 5] The semiconductor device, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 situated between elements 25 and 23)
and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 situated between elements 24 and 22)
wherein at least a portion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer (figure 4, col 10 lines 7-29, where element 1410 between elemenst 25 and 23 and between elements 24 and 22 is in contact with element 1410 that surrounds the left-hand, right-hand and top sides of elements 25 and 24).
[claim 9] The semiconductor device, wherein a lower surface of the second portion of the first gate cut is in contact with each of the first bottom gate electrode and the second bottom gate electrode (figure 18, col 24 lines 8-39, where the bottom portion of the second portion of element 1410 [first gate cut] is in contact with elements 33 and 32 [first and second bottom gate electrodes]).
[claim 10] The semiconductor device of claim 1, wherein a first material of the first portion of the first gate cut is different from a second material of the second portion of the first gate cut (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 combined make up the first gate cut and the first portion is element 1330 and 1410 and the second portion is element 1720. The materials can be made of different dielectric materials, thus having each material be distinct from one another).
[claim 11] The semiconductor device of claim 10, wherein an upper surface of the first portion of the first gate cut is in contact with a lower surface of the second portion of the first gate cut (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 combined make up the first gate cut and the first portion is element 1330 and 1410 and the second portion is element 1720. The bottom surface of the second portion is in contact with the upper surface of the first portion).
[claim 12] The semiconductor device of claim 10, wherein the second portion of the first gate cut surrounds sidewalls of the first portion of the first gate cut between the first upper gate electrode and the second upper gate electrode (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 and 1410 combined make up the first gate cut and the first portion is element 1330 and the second portion is element 1720. Where element 1410 of the first gate cut wraps around the sidwalls of the first portion between the two electrodes [region where 1410 intersects 1330]).
PNG
media_image1.png
679
665
media_image1.png
Greyscale
Figure 1: From figure 18 of Smith et al (US 10833078).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Smith et al (US 10833078 B2) in view of Huang et al (US 20210407999 A1).
Smith et al teaches all of the limitations of the parent claim, claims 1 and however, Smith et al does not specifically disclose
[claim 4] The semiconductor device, wherein the second portion of the first gate cut is in contact with each of the plurality of first upper nanosheets and the plurality of second upper nanosheets.
However, Huang et al does teach
[claim 4] The semiconductor device, wherein the second portion of the first gate cut is in contact with each of the plurality of first upper nanosheets and the plurality of second upper nanosheets (figure 2, paragraph 0037, where element 201 is the gate cut [section between the two gates mapped onto the gate cut of Lee et al], and the second portion [portion below middle element 203 in the top gate portion] touches the upper and lower nanosheets [nanoribbons in Huang et al, specifically]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Smith et al to include the teachings of Huang et al to incorporate nanoribbons surrounded by the gate electrodes to maximize the surface area to volume ratio, thus making the device more efficient.
Claim(s) 6-7 is rejected under 35 U.S.C. 103 as being unpatentable over Smith et al (US 10833078 B2) in view of Lee et al (US 20080001230 A1) in view of Huang et al (US 20210407999 A1).
Smith et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 6] The semiconductor device of claim 1, further comprising: a first bottom source/drain region disposed on a first side of the second bottom gate electrode on the second active pattern; an interlayer insulating layer on the first bottom source/drain region;a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the first bottom source/drain region; anda first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction, the first through via being overlapped with the second portion of the first gate cut in the first direction.
[claim 7] The semiconductor device of claim 6, further comprising: a second bottom source/drain region disposed on a first side of the first bottom gate electrode on the first active pattern; a second bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the second bottom source/drain region; and a second through via coupled to the second bottom source/drain contact by passing through the interlayer insulating layer in the third direction, the second through via being overlapped with the second portion of the first gate cut in the first direction.
However, Lee et al does teach
[claim 6] The semiconductor device of claim 1, further comprising: a first bottom source/drain region disposed on a first side of the second bottom gate electrode on the second active pattern (figure 7, paragraph 0027-0028, 0032, where element 167s is the first bottom source/drain region disposed on a first side of the second bottom gate electrode on the second active pattern, where element 155 on the right-hand side is the second bottom gate electrode on the second active pattern);
an interlayer insulating layer on the first bottom source/drain region (figure 7, paragraph 0037, element 166 is the interlayer insulating layer above the first bottom source drain region, element 167s);
a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the first bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction (figure 3 above, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s on the right-hand side of the right-hand side bottom electrode element 155] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
[claim 7] The semiconductor device of claim 6, further comprising: a second bottom source/drain region disposed on a first side of the first bottom gate electrode on the first active pattern (paragraph 0036, figure 7, where element 167d is the second source/drain region on a side of the first bottom gate electrode on the first active pattern (element 155 on the left-hand side of the figure]),
a second bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the second bottom source/drain region (figure 7, paragraph 0036, element 166 is the interlayer insulating layer, where element 169d is the source/drain contact disposed in the insulating layer),
and a second through via coupled to the second bottom source/drain contact by passing through the interlayer insulating layer in the third direction, the second through via being overlapped with the second portion of the first gate cut in the first direction (paragraph 0036, figure 7, element 175 is the through via coupled to the second bottom source/drain contact [element 169d], overlapping a second portion of the fist gate cut [are between elements 155], where element 175 overlaps said region between the two gate electrodes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Smith et al to incorporate the teachings of Lee et al in order to connect the transistors with through vias to allow for connection and operation of the transistors in a efficient manner.
However, Smith et al as modified by Lee et al still does not specifically disclose
[claim 6] the first through via being overlapped with the second portion of the first gate cut in the first direction.
However, Huang et al does teach
[claim 6] the first through via being overlapped with the second portion of the first gate cut in the first direction (paragraph 0039, figure 4, element 218 is the through via in place of the through via of figure 7 of Lee et al [element 184], and the through via overlaps an area in the first direction of the first gate cut [element 201 of Huang et al replacing the region between the gate electrodes of Lee et al, specifically figure 7 where the electrodes are elements 155 and 157]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Smith et al as modified to include the teachings of Huang et al to incorporate nanoribbons surrounded by the gate electrodes to maximize the surface area to volume ratio, thus making the device more efficient.
Claim(s) 13-20 is rejected under 35 U.S.C. 103 as being unpatentable over Smith et al (US 10833078 B2) in view of Lee et al (US 20080001230 A1).
Regarding claim 13,
Smith et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 13] wherein a first sidewall of the first portion of the first gate cut, which is in contact with the first bottom gate electrode, has an inclined profile with respect to a second sidewall of the second portion of the first gate cut, which is in contact with the first upper gate electrode.
Lee et al teaches
[claim 13] The semiconductor device, wherein a first sidewall of the first portion of the first gate cut, which is in contact with the first bottom gate electrode, has an inclined profile with respect to a second sidewall of the second portion of the first gate cut, which is in contact with the first upper gate electrode (figure 7, where the curved nature of the lower electrodes [specifically portion 151 of element 155a] creates an inclined surface, which contains the first portion of the first gate cut, and is contact with the first bottom gate electrode, when compared to the second portion of the first gate contact which is the portion with a flat side-wall [i.e. completely vertical]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Smith et al to incorporate the teachings of Lee et al in order to have an inclined surface to maximize efficiency of a particular use of the gate.
Regarding claims 14 and 20,
Smith et al teaches
[claim 14] A semiconductor device, comprising: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second direction different from the first direction (figure 4, col 10 lines 7-44, where elements 25 and 23 comprise the first active pattern and it extends into the page [called z-direction], which is the first direction. Elements 22 and 24 comprise the second active pattern and extends in the first direction [into the page], and is spaced apart from the first active pattern in a second direction [x-direction], which is different than the first direction);
a first bottom gate electrode extended in the second direction on the first active pattern (figure 17, col 21 line 49 – col 22 line 4, where element 33 is the first bottom gate electrode and is situated over the first active region [element 23], and extends in a second direction [x-direction]);
a first upper gate electrode extended in the second direction on the first bottom gate electrode, the first upper gate electrode being spaced apart from the first bottom gate electrode in a third direction (figure 17, col 21 line 49 – col 22 line 4, where element 35 is the first upper gate electrode and extends in a second direction [x-direction] and the first gate electrode [element 35] is separated from the first bottom gate electrode [element 33] by a third direction [y-direction]),
a second bottom gate electrode extended in the second direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second direction (figure 17, col 21 line 49 – col 22 line 4, where element 32 is the second bottom gate electrode on the second active pattern [element 22] and extends in a second direction [x-direction] and spaced apart from the first bottom gate electrode [element 33] in a second direction [x-direction]);
a second upper gate electrode extended in the second direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the third direction (figure 17, col 21 line 49 – col 22 line 4, where element 34 is the second upper gate electrode and extends in a second direction [x-direction] and the second gate electrode [element 34] is separated from the second bottom gate electrode [element 32] by a third direction [y-direction]),
the second upper gate electrode being spaced apart from the first upper gate electrode in the second direction (figure 4, col 21 line 49 – col 22 line 4, where element 35 is the first upper gate electrode and element 34 is the second upper electrode and they are separated by each other in the second direction [x-direction]),
a gate cut comprising a first portion isolating the 'first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode (figure 4, col 10 lines 7-44, where element 1410 is the gate cut, comprising a first portion located on the left-hand side, right-hand side and the middle of the first and second bottom electrode [elements 33 and 32], and a second portion on the left-hand side, right-hand side and between the first and second top electrode [elements 35 and 34]).
[claim 20] A semiconductor device, comprising: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second direction different from the first direction (figure 4, col 10 lines 7-44, where elements 25 and 23 comprise the first active pattern and it extends into the page [called z-direction], which is the first direction. Elements 22 and 24 comprise the second active pattern and extends in the first direction [into the page], and is spaced apart from the first active pattern in a second direction [x-direction], which is different than the first direction),
a first bottom gate electrode extended in the second direction on the first active pattern (figure 17, col 21 line 49 – col 22 line 4, where element 33 is the first bottom gate electrode and is situated over the first active region [element 23], and extends in a second direction [x-direction]),
a first upper gate electrode extended in the second direction on the first bottom gate electrode, the first upper gate electrode being spaced apart from the first bottom gate electrode in the third direction (figure 17, col 21 line 49 – col 22 line 4, where element 35 is the first upper gate electrode and extends in a second direction [x-direction] and the first gate electrode [element 35] is separated from the first bottom gate electrode [element 33] by a third direction [y-direction]),
a second bottom gate electrode extended in the second direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second direction (figure 17, col 21 line 49 – col 22 line 4, where element 32 is the second bottom gate electrode on the second active pattern [element 22] and extends in a second direction [x-direction] and spaced apart from the first bottom gate electrode [element 33] in a second direction [x-direction]),
a second upper gate electrode extended in the second direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the third direction, the second upper gate electrode being spaced apart from the first upper gate electrode in the second direction (figure 17, col 21 line 49 – col 22 line 4, where element 34 is the second upper gate electrode and extends in a second direction [x-direction] and the second gate electrode [element 34] is separated from the second bottom gate electrode [element 32] by a third direction [y-direction], and is separated from the first upper gate electrode [element 35] in the second direction [x-direction]);
a gate cut including a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode, wherein a width in the second direction of the second portion of the gate cut exceeds a width in the second direction of the first portion of the gate cut (figure 4, col 10 lines 7-44, where element 1410 is the gate cut, comprising a first portion located on the left-hand side, right-hand side and the middle of the first and second bottom electrode [elements 33 and 32], and a second portion on the left-hand side, right-hand side and between the first and second top electrode [elements 35 and 34], where element 1410 is the gate cut and has a second portion surrounding the top gate electrodes [elements 35 and 34] where there the cut in the second direction [x-direction] is greater than the first portion in the second direction, specifically element 1410 that surrounds the bottom gate electrodes [elements 33 and 32]).
a plurality of first bottom nanosheets stacked spaced apart from each other in a third direction on the first active pattern, the first bottom gate electrode surrounding the plurality of first bottom nanosheets (figure 4, col 12, lines 38-49, where element 23 is the first bottom nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the first active patter [element 23 pattern], where it is surrounded by the first lower gate electrode [element 33]);
a plurality of first upper nanosheets stacked spaced apart from each other in the third direction on the plurality of first bottom nanosheets, the first upper gate electrode surrounding the plurality of first upper nanosheets (figure 4, col 12, lines 38-49, where element 25 is the first upper nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the first active patter [element 25 pattern], where it is surrounded by the first upper gate electrode [element 35]);
a plurality of second bottom nanosheets stacked spaced apart from each other in the third direction on the second active pattern, the second bottom gate electrode surrounding the plurality of second bottom nanosheets (figure 4, col 12, lines 38-49, where element 22 is the second bottom nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the second active patter [element 22 pattern], where it is surrounded by the second lower gate electrode [element 32]);
a plurality of second upper nanosheets stacked spaced apart from each other in the third direction on the plurality of second bottom nanosheets the second upper gate electrode surrounding the plurality of second upper nanosheets (figure 4, col 12, lines 38-49, where element 24 is the second upper nanosheets and comprises a stack of nanosheets stacked in the third direction [y-direction] on the second active patter [element 24 pattern], where it is surrounded by the second upper gate electrode [element 34]);
However, Smith et al does not specifically disclose
[claim 14] a first bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern; an interlayer insulating layer on the first bottom source/drain region; a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the 'first bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction, the first through via being non- overlapped with the first upper gate electrode in the first direction.
[claim 20] a bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern; an interlayer insulating layer on the first bottom source/drain region; a bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction, the through via being overlapped with the second portion of the gate cut in the first direction.
However, Lee et al does teach
[claim 14] a first bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern (figure 3 below, figure 6A of Lee et al, where element 167 is the first bottom source/drain region on one side of the first bottom gate electrode [element 155a] in the first active region);
an interlayer insulating layer on the first bottom source/drain region (figure 3 below, where element 166 above element 167s is the first interlayer insulating layer on the first bottom source/drain region);
a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the 'first bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction (figure 3 below, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
the first through via being non- overlapped with the first upper gate electrode in the first direction (figure 3 below, figure 7 of Lee et al, where element 184 does not overlap the first upper gate electrode [element 155]).
[claim 20] a bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern (figure 3 below, figure 6A of Lee et al, where element 167 is the first bottom source/drain region on one side of the first bottom gate electrode [element 155a] in the first active region);
an interlayer insulating layer on the first bottom source/drain region (figure 3 below, where element 166 above element 167s is the first interlayer insulating layer on the first bottom source/drain region);
a bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the third direction (figure 3 below, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
the through via being overlapped with the second portion of the gate cut in the first direction (figure 3 below, figure 7 of Lee et al, where element 184 does not overlap the first upper gate electrode [element 155]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Smith et al to incorporate the teachings of Lee et al to connect the source/drain to through vias to form a functioning transistor for outside circuits that may connect to it.
However, Smith et al as modified does not specifically disclose
[claim 14] wherein a pitch in the second direction between the first upper gate electrode and the second upper gate electrode exceeds a pitch in the second direction between the 'first bottom gate electrode and the second bottom gate electrode.
However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Smith et al as modified to incorporate routine optimization as there are only three distinct relative pitches that can take place: the upper gates have a pitch greater than, equal to, lower than the pitch of the lower gates. In the present disclosure the gate electrodes are of equal pitch, but through optimization it may be more beneficial to have the pitch of the upper gate electrodes to be greater than the lower gate electrodes for specific use purposes of the design of the transistors in an application.
Regarding claims 15-18,
Smith et al further teaches
[claim 15] The semiconductor device of claim14, wherein a width in the second direction of the second portion of the gate cut exceeds a width in the second direction of the first portion of the gate cut, and wherein the second portion of the gate cut overlaps at least one of the first bottom gate electrode and the second bottom gate electrode in the third direction (figure 4, col 10 lines 7-44, where element 1410 is the gate cut and has a second portion surrounding the top gate electrodes [elements 35 and 34] where there the cut in the second direction [x-direction] is greater than the first portion in the second direction, specifically element 1410 that surrounds the bottom gate electrodes [elements 33 and 32]).
[claim 16] The semiconductor device of claim15, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the left-hand side, being mapped onto the left-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);
and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the right-hand side, being mapped onto the right-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);,
wherein at least a portion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer (figure 4, col 10 lines 7-29, where element 1720 is the first gate cut and maps onto the first gate cut between electrodes of Lee et al, and stretches from the top of the device until the bottom of element 1410, and contacts both isolation layers [element 1410 on either side of the first gate cut], and element 1330 is the second gate cut).
[claim 17] The semiconductor device of claim 15, wherein a lower surface of the second portion of the gate cut is in contact with each of the 'first bottom gate electrode and the second bottom gate electrode (figure 4, col 10 lines 7-44, where the lower surface of element 1410 that surrounds the top gate electrodes [elements 35 and 34] contacts the first and second bottom gate electrodes [elements 33 and 32]).
[claim 18] The semiconductor device of claim 15, wherein a first material of the first portion of the gate cut is different from a second material of the second portion of the gate cut (figure 4, col 10 lines 7-29, where element 1330 and element 1720 make up the first gate cut and can be made of different dielectric materials).
Regarding claim 19,
Smith et al as modified teaches all fo the limitations of the parent claim, claim 14, but does not specifically disclose
[claim 19] The semiconductor device of claim 14, further comprising: a second bottom source/drain region disposed on one side of the second bottom gate electrode on the second active pattern, and a second through via coupled to the second bottom source/drain region by passing through the interlayer insulating layer in the third direction, the second through via being non-overlapped with the second upper gate electrode in the first direction.
However, Lee et al does teach
[claim 19] The semiconductor device of claim 14, further comprising: a second bottom source/drain region disposed on one side of the second bottom gate electrode on the second active pattern (figure 7, element 167s is on one side of the second bottom gate electrode [element 155a]),
and a second through via coupled to the second bottom source/drain region by passing through the interlayer insulating layer in the third direction, the second through via being non-overlapped with the second upper gate electrode in the first direction (figure 7, paragraph 0035, where element 183 and the item directly below it above the second bottom source/drain [element 167s] is the through via coupled to the bottom source/drain layer by passing through the interlayer [element 166] to get to said source/drain layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Smith et al as modified to incorporate the teachings of Lee et al in order to connect the source and drain to through vias to connect the transistor to outside devices to use the transistors in functioning circuits.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights