Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “a pitch of the upper and lower gate electrodes being different” must be shown or the feature(s) canceled from the claim(s). As drawings do not show a pitch of the upper and lower gate electrodes being different, the drawings appear to show the same pitch. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 14, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 14, and 20, the terminology “second horizontal direction” is ambiguous as the disclosure defines this to mean a direction within a plan of two separate directions (i.e. in the x-y plane, one direction is in the x-direction and the “second horizontal” direction is in the y-direction). Whereas, a normal reading of the terminology would assume a first horizontal direction is only in the positive or negative x-direction, and the second is necessarily in the opposite direction. According to a normal reading of the terminology, the claim is rendered indefinite because one cannot extend in a first horizontal direction [i.e. positive x-direction] and then also be spaced apart in a second horizontal direction different than the first [i.e. negative horizontal direction] without designating a point of reference, as any two-dimensional object [as claimed here] necessarily extends in both the first and second horizontal direction [the nature of having a width and height]. Thus, it is recommended the applicant designate a first, second, and third direction and state how they are related, at least in the specification. Usually the first is orthogonal to the second, the third is then orthogonal to the first and second, thus creating a standard 3-dimensional reference space. In the current rejection, the understanding [to match up with the specification] is that the first horizontal direction is the x-direction, the second horizontal direction is the y-direction and the vertical direction is the z-direction, where all three directions are orthogonal to one another.
Claims 2-13 and 15-19 further limit independent claims 1 and 14, therefore, are unclear for the same reasons described above.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 20080001230 A1).
Lee et al teaches
[claim 1] A semiconductor device, comprising: a first active pattern extended in a first horizontal direction on a substrate; a second active pattern extended in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction (figure 1 below, figures 1 and 6A of Lee et al, paragraphs 0027-0028 and 0032, where element “A” is the active region, and corresponds to region 168 of figure 6A [high density channel impurity region], where each oval shape in figure 1 labeled “A” is an active pattern, of which there are 5. The first direction is the y-direction [labeled below in Figure 1], and the second horizontal direction is the x-direction [labeled below in figure 1]. The first active pattern is the pattern labeled “A” and extends in the y-direction. A second active pattern [labeled below] extends in the second horizontal direction [x-direction]. Where the second active pattern is spaced apart from the first active portion in the x-direction [i.e. it is situated below in the x-direction of the active region labeled “A”]),
a first bottom gate electrode extended in the second horizontal direction on the first active pattern (figure 1 below, paragraph 0029, where element LG is the first bottom gate electrode and extends in the x-direction [second direction]);
a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode, the first upper gate electrode being spaced apart from the first bottom gate electrode in a vertical direction (figure 1 below, paragraph 0029, figures 1 and 6A of Lee et al, where element LG is the first lower gate electrode, element UG is the first upper gate electrode and both extend in the x-direction [second direction]. Per figure 6A, element 157 is the upper gate electrode, and element 155 is the lower gate electrode and such are stacked in the vertical [z-direction/third direction]);
a second bottom gate electrode extended in the second horizontal direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second horizontal direction (figure 1 below, where the second lower gate electrode is situated in a more negative x-direction than the first lower gate electrode, and the second bottom gate electrode extends in the second direction [x-directon] on the second active pattern);
second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the vertical direction, the second upper gate electrode being spaced apart from the first upper gate electrode in the second horizontal direction (figure 1 below, where the second upper gate electrode extends in the second direction [x-direction] on the second bottom gate electrode, the second upper gate electrode is spaced apart from the second bottom gate electrode in the vertical direction [as seen in figure 6A, where element 155 is the lower gate electrode, and element 157 is the upper gate electrode], and spaced apart from each other in the second direction [x-direction, as shown below in figure 1]);
and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode, wherein a width in the second horizontal direction of the second portion of the first gate cut exceeds a width in the second horizontal direction of the first portion of the first gate cut, and wherein the second portion of the first gate cut overlaps at least one of the first bottom gate electrode and the second bottom gate electrode in the vertical direction (see figure 2, figure 6A, paragraphs 0026-0027, where the first gate cut is the area confined by element 168 which separates the first and second lower gate electrode, the second gate cut is the section between elements 154 and 157a, and is a width that is greater than the width of the first gate cut, and additionally covers part of the lower gate electrode [note element 154 is part of the lower gate electrode but also overlaps with the second gate cut portion]).
[claim 9] The semiconductor device, wherein a lower surface of the second portion of the first gate cut is in contact with each of the first bottom gate electrode and the second bottom gate electrode (figure 7, where the lower surface of the second portion of the first gate cut [section between 154 and 157 between the two lower gate electrodes] contacts both the first and second bottom gate electrode [both elements 155a]).
[claim 13] The semiconductor device, wherein a first sidewall of the first portion of the first gate cut, which is in contact with the first bottom gate electrode, has an inclined profile with respect to a second sidewall of the second portion of the first gate cut, which is in contact with the first upper gate electrode (figure 7, where the curved nature of the lower electrodes [specifically portion 151 of element 155a] creates an inclined surface, which contains the first portion of the first gate cut, and is contact with the first bottom gate electrode, when compared to the second portion of the first gate contact which is the portion with a flat side-wall [i.e. completely vertical]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 15, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20080001230 A1).
Lee et al teaches
[claim 14] A semiconductor device, comprising: a first active pattern extended in a first horizontal direction on a substrate; a second active pattern extended in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction (figure 1 below, paragraphs 0027-0028 figure 1 from Lee et al, where the first active pattern is shown extending in a the first direction [y-direction] and the second active pattern shown below also extends in the first direction [y-direction] and is separated from the first active portion in the second direction [x-direction]);
a first bottom gate electrode extended in the second horizontal direction on the first active pattern; a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode (figure 1 below, paragraphs 0027-0028, where the first bottom gate electrode shown in the image [LG] extends in the second direction [x-direction] on the first active pattern, and the first upper gate electrode [UG] also extends in a second direction [x-direction] and is on the first bottom gate electrode),
the first upper gate electrode being spaced apart from the first bottom gate electrode in a vertical direction (figure 6A, paragraph 0027, where element 155 is the lower gate electrode and element 157a is the upper gate electrode and is spaced apart in the vertical direction [z-direction] from the lower gate electrode);
a second bottom gate electrode extended in the second horizontal direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second horizontal direction (figure 1 below, paragraphs 0027-0028, where the first bottom gate electrode shown in the image [LG] extends in the second direction [x-direction] on the first active pattern, and the first upper gate electrode [UG] also extends in a second direction [x-direction] and is on the first bottom gate electrode);
a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the vertical direction (figure 1 below, figures 1 and 6A of Lee et al, paragraphs 0027-0028, and 0032 where the second upper gate electrode [shown below] extends in the second direction [x-direction] over the second bottom gate electrode [shown below], the second bottom gate electrode in figure 6A is the other gate electrode represented by element 155 but not labeled, and the second upper gate electrode is element 157a not labeled, and is separated from the second bottom gate electrode in the vertical direction [z-direction]),
the second upper gate electrode being spaced apart from the first upper gate electrode in the second horizontal direction (figure 1 below, second upper gate electrode is spaced apart from first upper gate electrode in the second direction [x-direction]);
a first bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern (figure 3 below, figure 6A of Lee et al, where element 167 is the first bottom source/drain region on one side of the first bottom gate electrode [element 155a] in the first active region);
an interlayer insulating layer on the first bottom source/drain region (figure 3 below, where element 166 above element 167s is the first interlayer insulating layer on the first bottom source/drain region);
a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the 'first bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the vertical direction (figure 3 below, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
the first through via being non- overlapped with the first upper gate electrode in the first horizontal direction (figure 3 below, figure 7 of Lee et al, where element 184 does not overlap the first upper gate electrode [element 155]),
However, Lee et al does not specifically disclose
[claim 14] wherein a pitch in the second horizontal direction between the first upper gate electrode and the second upper gate electrode exceeds a pitch in the second horizontal direction between the 'first bottom gate electrode and the second bottom gate electrode.
However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to incorporate routine optimization as there are only three distinct relative pitches that can take place: the upper gates have a pitch greater than, equal to, lower than the pitch of the lower gates. In the present disclosure the gate electrodes are of equal pitch, but through optimization it may be more beneficial to have the pitch of the upper gate electrodes to be greater than the lower gate electrodes for specific use purposes of the design of the transistors in an application.
Lee et al further teaches
[claim 15] The semiconductor device of claim14, further comprising: a gate cut comprising a first portion isolating the 'first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode, wherein a width in the second horizontal direction of the second portion of the gate cut exceeds a width in the second horizontal direction of the first portion of the gate cut, and wherein the second portion of the gate cut overlaps at least one of the first bottom gate electrode and the second bottom gate electrode in the vertical direction (see figure 2 below, figure 6A, paragraphs 0026-0027, where the first gate cut is is the area confined by element 168 which separates the first and second lower gate electrode, the second gate cut is the section between elements 154 and 157a, and is a width that is greater than the width of the first gate cut, and additionally covers part of the lower gate electrode [note element 154 is part of the lower gate electrode but also overlaps with the second gate cut portion in the vertical direction [[z-direction]]]).
[claim 17] The semiconductor device of claim 15, wherein a lower surface of the second portion of the gate cut is in contact with each of the 'first bottom gate electrode and the second bottom gate electrode (figure 7, paragraphs 0027-0028, 0032 where the lower surface of the second portion of the gate cut [between element 154 and 151 between the two electrodes] are in contact with each bottom electrode [since element 154 is part of the lower electrode]).
[claim 19] The semiconductor device of claim 14, further comprising: a second bottom source/drain region disposed on one side of the second bottom gate electrode on the second active pattern (figure 7, element 167s is on one side of the second bottom gate electrode [element 155a]),
and a second through via coupled to the second bottom source/drain region by passing through the interlayer insulating layer in the vertical direction, the second through via being non-overlapped with the second upper gate electrode in the first horizontal direction (figure 7, paragraph 0035, where element 183 and the item directly below it above the second bottom source/drain [element 167s] is the through via coupled to the bottom source/drain layer by passing through the interlayer [element 166] to get to said source/drain layer).
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Figure 1: From Figure 1 of Lee et al (US 20080001230 A1).
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Figure 2: From figure 6A i Lee et al (US 20080001230 A1).
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Figure 3: From Figure 7 of Lee et al (US 20080001230 A1).
Claim(s) 2-7, 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20080001230 A1) in view of Huang et al (US 20210407999 A1) and Smith et al (US 10833078 B2).
Lee et al teaches all of the limitations of the parent claims, claims 1 and 14, as well as
[claim 6] The semiconductor device of claim 1, further comprising: a first bottom source/drain region disposed on a first side of the second bottom gate electrode on the second active pattern (figure 7, paragraph 0027-0028, 0032, where element 167s is the first bottom source/drain region disposed on a first side of the second bottom gate electrode on the second active pattern, where element 155 on the right-hand side is the second bottom gate electrode on the second active pattern);
an interlayer insulating layer on the first bottom source/drain region (figure 7, paragraph 0037, element 166 is the interlayer insulating layer above the first bottom source drain region, element 167s);
a first bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the first bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the vertical direction (figure 3 above, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s on the right-hand side of the right-hand side bottom electrode element 155] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
[claim 7] The semiconductor device of claim 6, further comprising: a second bottom source/drain region disposed on a first side of the first bottom gate electrode on the first active pattern (paragraph 0036, figure 7, where element 167d is the second source/drain region on a side of the first bottom gate electrode on the first active pattern (element 155 on the left-hand side of the figure]),
a second bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the second bottom source/drain region (figure 7, paragraph 0036, element 166 is the interlayer insulating layer, where element 169d is the source/drain contact disposed in the insulating layer),
and a second through via coupled to the second bottom source/drain contact by passing through the interlayer insulating layer in the vertical direction, the second through via being overlapped with the second portion of the first gate cut in the first horizontal direction (paragraph 0036, figure 7, element 175 is the through via coupled to the second bottom source/drain contact [element 169d], overlapping a second portion of the fist gate cut [are between elements 155], where element 175 overlaps said region between the two gate electrodes).
[claim 20] A semiconductor device, comprising: a first active pattern extended in a first horizontal direction on a substrate; a second active pattern extended in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction (figure 1 above, figures 1 and 6A of Lee et al, paragraphs 0027-0028 and 0032, where element “A” is the active region, and corresponds to region 168 of figure 6A [high density channel impurity region], where each oval shape in figure 1 labeled “A” is an active pattern, of which there are 5. The first direction is the y-direction [labeled above in Figure 1], and the second horizontal direction is the x-direction [labeled above in figure 1]. The first active pattern is the pattern labeled “A” and extends in the y-direction. A second active pattern [labeled above] extends in the second horizontal direction [x-direction]. Where the second active pattern is spaced apart from the first active portion in the x-direction [i.e. it is situated below in the x-direction of the active region labeled “A”]),
a first bottom gate electrode extended in the second horizontal direction on the first active pattern (figure 1 above, first bottom gate electrode is labeled and extends in a second direction [x-direction] on the first active pattern),
a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode (figure 1 above, first upper gate electrode extends in the second direction [x-direction] on the first active pattern),
the first upper gate electrode being spaced apart from the first bottom gate electrode in the vertical direction (figure 2 above, paragraphs 0027-0028, 0032 where the first upper gate electrode is element 157 and is vertically [z-direction] spaced from the bottom electrode, element 155),
a second bottom gate electrode extended in the second horizontal direction on the second active pattern, the second bottom gate electrode being spaced apart from the first bottom gate electrode in the second horizontal direction (figure 1 above, where the second bottom gate electrode [as labeled] extends in the second direction [x-direction] on the second active pattern, and spaced from the first bottom gate electrode in the second direction [x-direction]),
a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, the second upper gate electrode being spaced apart from the second bottom gate electrode in the vertical direction, the second upper gate electrode being spaced apart from the first upper gate electrode in the second horizontal direction (figure 1 above, paragraphs 0027-0028, 0032, where the second upper gate electrode extends in a second direction [x-direction] over the second bottom gate electrode and is spaced apart from the second bottom gate electrode in the vertical direction [see figure 2 above, element 157 is spaced apart from 155 in the vertical, z, direction], and spaced apart from the first upper gate electrode in the second direction [x-direction]),
a gate cut including a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode, wherein a width in the second horizontal direction of the second portion of the gate cut exceeds a width in the second horizontal direction of the first portion of the gate cut. (see figure 2 above, figure 6A, paragraphs 0026-0027, where the first gate cut is is the area confined by element 168 which separates the first and second lower gate electrode, the second gate cut is the section between elements 154 and 157a, and is a width that is greater than the width of the first gate cut, and additionally covers part of the lower gate electrode [note element 154 is part of the lower gate electrode but also overlaps with the second gate cut portion]).;
a bottom source/drain region disposed on one side of the first bottom gate electrode on the first active pattern (figure 3 below, figure 6A of Lee et al, where element 167 is the first bottom source/drain region on one side of the first bottom gate electrode [element 155a] in the first active region);
an interlayer insulating layer on the first bottom source/drain region (figure 3 below, where element 166 above element 167s is the first interlayer insulating layer on the first bottom source/drain region);
a bottom source/drain contact disposed inside the interlayer insulating layer and coupled to the bottom source/drain region; and a first through via coupled to the first bottom source/drain contact by passing through the interlayer insulating layer in the vertical direction (figure 3 below, figure 7 of Lee et al, where element 184 is the first through via coupled to the first bottom source/drain contact [element 167s] through the contact situated between element 184 and element 167s surrounded by the interlayer insulating layer [element 166]),
However, Lee et al does not specifically disclose
[claim 2] The semiconductor device further comprising: a plurality of first bottom nanosheets stacked in the vertical direction on the first active pattern, the plurality of first bottom nanosheets being spaced apart from each other in the vertical direction, the plurality of first bottom nanosheets being surrounded by the first bottom gate electrode;a plurality of first upper nanosheets stacked in the vertical direction on the plurality of first bottom nanosheets, the plurality of first upper nanosheets being spaced apart from each other in the vertical direction, the plurality of first upper nanosheets being surrounded by the first upper gate electrode; a plurality of second bottom nanosheets stacked in the vertical direction on the second active pattern, the plurality of second bottom nanosheets being spaced apart from each other in the vertical direction, the plurality of second bottom nanosheets being surrounded by the second bottom gate electrode; and a plurality of second upper nanosheets stacked in the vertical direction on the plurality of second bottom nanosheets, the plurality of second upper nanosheets being spaced apart from each other in the vertical direction, the plurality of second upper nanosheets being surrounded by the second upper gate electrode.
[claim 3] The semiconductor device, further comprising: a first isolation layer disposed between the plurality of first bottom nanosheets and the plurality of first upper nanosheets; and a second isolation layer disposed between the plurality of second bottom nanosheets and the plurality of second upper nanosheets.
[claim 4] The semiconductor device, wherein the second portion of the first gate cut is in contact with each of the plurality of first upper nanosheets and the plurality of second upper nanosheets.
[claim 5] The semiconductor device, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode; and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode, wherein at least aportion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer.
[claim 6] the first through via being overlapped with the second portion of the first gate cut in the first horizontal direction.
[claim 20] a plurality of first bottom nanosheets stacked spaced apart from each other in a vertical direction on the first active pattern; a plurality of first upper nanosheets stacked spaced apart from each other in the vertical direction on the plurality of first bottom nanosheets; a plurality of second bottom nanosheets stacked spaced apart from each other in the vertical direction on the second active pattern; a plurality of second upper nanosheets stacked spaced apart from each other in the vertical direction on the plurality of second bottom nanosheets; the first bottom gate electrode surrounding the plurality of first bottom nanosheets; the first upper gate electrode surrounding the plurality of first upper nanosheets; the second bottom gate electrode surrounding the plurality of second bottom nanosheets; the second upper gate electrode surrounding the plurality of second upper nanosheets; the through via being overlapped with the second portion of the gate cut in the first horizontal direction,
However, Huang et al does teach
[claim 2] The semiconductor device further comprising: a plurality of first bottom nanosheets stacked in the vertical direction on the first active pattern, the plurality of first bottom nanosheets being spaced apart from each other in the vertical direction, the plurality of first bottom nanosheets being surrounded by the first bottom gate electrode (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the lower left-hand side, surrounded by the first lower gate electrode, element 208);
a plurality of first upper nanosheets stacked in the vertical direction on the plurality of first bottom nanosheets, the plurality of first upper nanosheets being spaced apart from each other in the vertical direction, the plurality of first upper nanosheets being surrounded by the first upper gate electrode (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the upper left-hand side, surrounded by the first upper gate electrode, element 204);;
a plurality of second bottom nanosheets stacked in the vertical direction on the second active pattern, the plurality of second bottom nanosheets being spaced apart from each other in the vertical direction, the plurality of second bottom nanosheets being surrounded by the second bottom gate electrode (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the lower right-hand side, surrounded by the second lower gate electrode, element 208);
and a plurality of second upper nanosheets stacked in the vertical direction on the plurality of second bottom nanosheets, the plurality of second upper nanosheets being spaced apart from each other in the vertical direction, the plurality of second upper nanosheets being surrounded by the second upper gate electrode (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the upper right-hand side, surrounded by the second upper gate electrode, element 204).
[claim 4] The semiconductor device, wherein the second portion of the first gate cut is in contact with each of the plurality of first upper nanosheets and the plurality of second upper nanosheets (figure 2, paragraph 0037, where element 201 is the gate cut [section between the two gates mapped onto the gate cut of Lee et al], and the second portion [portion below middle element 203 in the top gate portion] touches the upper and lower nanosheets [nanoribbons in Huang et al, specifically]).
[claim 6] the first through via being overlapped with the second portion of the first gate cut in the first horizontal direction (paragraph 0039, figure 4, element 218 is the through via in place of the through via of figure 7 of Lee et al [element 184], and the through via overlaps an area in the horizontal direction of the first gate cut [element 201 of Huang et al replacing the region between the gate electrodes of Lee et al, specifically figure 7 where the electrodes are elements 155 and 157]).
[claim 20] a plurality of first bottom nanosheets stacked spaced apart from each other in a vertical direction on the first active pattern; a plurality of first upper nanosheets stacked spaced apart from each other in the vertical direction on the plurality of first bottom nanosheets (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the lower and upper left-hand side, surrounded by the first lower gate electrode, element 208, and first upper gate electrode, element 204 separated from each other in the vertical direction. They are situated in Lee et al on the first active region, in place of element 167s of figure 7);
a plurality of second bottom nanosheets stacked spaced apart from each other in the vertical direction on the second active pattern; a plurality of second upper nanosheets stacked spaced apart from each other in the vertical direction on the plurality of second bottom nanosheets (figure 2, paragraphs 0037-0038, where element 203 are the nanoribbons stacked in a vertical direction in the lower right-hand side, surrounded by the second lower gate electrode, element 208, and the second upper gate electrode, element 204, and spaced apart from each other in the vertical direction. They are situated in Lee et al on the first active region, in place of element 167s on the right hand side of the second gate electrode pair of figure 7);;
the first bottom gate electrode surrounding the plurality of first bottom nanosheets (figure 2, paragraphs 0037-0038, where element 208 in the lower left-hand side surround the first bottom nanosheets, element 203);
the first upper gate electrode surrounding the plurality of first upper nanosheets (figure 2, paragraphs 0037-0038, where element 204 in the upper left-hand side surround the first upper nanosheets, element 203);
the second bottom gate electrode surrounding the plurality of second bottom nanosheets (figure 2, paragraphs 0037-0038, where element 208 in the lower right-hand side surround the second bottom nanosheets, element 203);
the second upper gate electrode surrounding the plurality of second upper nanosheets (figure 2, paragraphs 0037-0038, where element 204 in the upper right-hand side surround the second upper nanosheets, element 203);
the through via being overlapped with the second portion of the gate cut in the first horizontal direction (paragraph 0039, figure 2, element 218 is the through via that overlaps the second part of the gate cut [element 201]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to include the teachings of Huang et al to incorporate nanoribbons surrounded by the gate electrodes to maximize the surface area to volume ratio, thus making the device more efficient.
However, Huang et al does not specifically disclose
[claim 3] The semiconductor device, further comprising: a first isolation layer disposed between the plurality of first bottom nanosheets and the plurality of first upper nanosheets; and a second isolation layer disposed between the plurality of second bottom nanosheets and the plurality of second upper nanosheets.
[claim 5] The semiconductor device, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode; and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode, wherein at least aportion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer.
[claims 2-5, 20] Nanosheets (in all places)
However, Smith et al does teach
[claim 3] The semiconductor device, further comprising: a first isolation layer disposed between the plurality of first bottom nanosheets and the plurality of first upper nanosheets (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the lefthand side, being mapped onto the left-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);
and a second isolation layer disposed between the plurality of second bottom nanosheets and the plurality of second upper nanosheets (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the right-hand side, being mapped onto the right-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);
[claim 5] The semiconductor device, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the left-hand side, being mapped onto the left-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);
and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the right-hand side, being mapped onto the right-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);,
wherein at least a portion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer (figure 4, col 10 lines 7-29, where element 1720 is the first gate cut and maps onto the first gate cut between electrodes of Lee et al, and stretches from the top of the device until the bottom of element 1410, and contacts both isolation layers [element 1410 on either side of the first gate cut], and element 1330 is the second gate cut).
[claims 2-5 20] nanosheets (instead of nanoribbons)
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified to incorporate the teachings of Smit et al to use nanosheets instead of nanoribbons to maximize even more the surface area to volume ratio of the regions thus creating a high level of efficiency for a device needed greater surface area than a nanoribbon or wire [which is one dimensional and not 2 dimensional in nature, like a nanosheet].
Claim(s) 10-12, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20080001230 A1) in view of Smith et al (US 10833078 B2).
Regarding claims 10-12, Lee et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 10] The semiconductor device of claim 1, wherein a first material of the first portion of the first gate cut is different froma second material of the second portion of the first gate cut.
[claim 11] The semiconductor device of claim 10, wherein an upper surface of the first portion of the first gate cut is in contact with a lower surface of the second portion of the first gate cut.
[claim 12] The semiconductor device of claim 10, wherein the second portion of the first gate cut surrounds sidewalls of the first portion of the first gate cut between the first upper gate electrode and the second upper gate electrode.
However, Smith et al does teach
[claim 10] The semiconductor device of claim 1, wherein a first material of the first portion of the first gate cut is different from a second material of the second portion of the first gate cut (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 combined make up the first gate cut and the first portion is element 1330 and 1410 and the second portion is element 1720. The materials can be made of different dielectric materials, thus having each material be distinct from one another).
[claim 11] The semiconductor device of claim 10, wherein an upper surface of the first portion of the first gate cut is in contact with a lower surface of the second portion of the first gate cut (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 combined make up the first gate cut and the first portion is element 1330 and 1410 and the second portion is element 1720. The bottom surface of the second portion is in contact with the upper surface of the first portion).
[claim 12] The semiconductor device of claim 10, wherein the second portion of the first gate cut surrounds sidewalls of the first portion of the first gate cut between the first upper gate electrode and the second upper gate electrode (figure 4, col 10 lines 7-29, where elements 1720, 1410, and 1330 and 1410 combined make up the first gate cut and the first portion is element 1330 and the second portion is element 1720. Where element 1410 of the first gate cut wraps around thesidwalls of the first portion between the two electrodes [region where 1410 intersects 1330]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to incorporate the teachings of Smith et al in order to use different dielectric materials between different shaped electrodes to adequately tailor the material to the needs of the electrodes to minimize parasitic capacitance and make the device overall more efficient and effective.
Regarding claims 16 and 18, Lee et al as modified above discloses all of the limitations of the parent claim, claim 15, but does not specifically disclose
[claim 16] The semiconductor device of claim15, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode, and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode; wherein at least a portion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer.
[claim 18] The semiconductor device of claim 15, wherein a first material of the first portion of the gate cut is different from a second material of the second portion of the gate cut.
However, Smith et al does teach
[claim 16] The semiconductor device of claim15, further comprising: a first gate isolation layer disposed between the first bottom gate electrode and the first upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the left-hand side, being mapped onto the left-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);
and a second gate isolation layer disposed between the second bottom gate electrode and the second upper gate electrode (figure 4, col 10 lines 30-44, where the first isolation layer is element 1410 on the right-hand side, being mapped onto the right-hand side gate electrodes and nanosheets of Huang et al [figure 2 specifically]);,
wherein at least a portion of a lower surface of the second portion of the first gate cut is in contact with the first gate isolation layer and the second gate isolation layer (figure 4, col 10 lines 7-29, where element 1720 is the first gate cut and maps onto the first gate cut between electrodes of Lee et al, and stretches from the top of the device until the bottom of element 1410, and contacts both isolation layers [element 1410 on either side of the first gate cut], and element 1330 is the second gate cut).
[claim 18] The semiconductor device of claim 15, wherein a first material of the first portion of the gate cut is different from a second material of the second portion of the gate cut (figure 4, col 10 lines 7-29, where element 1330 and element 1720 make up the first gate cut and can be made of different dielectric materials).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified to incorporate the teachings of Smit et al to include a gate isolation layer to maximize the effect of the gate electrode on the active regions by limiting the parasitic capacitance by increase separation between the conductive elements all while putting an isolation layer between them.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jhan et al (US 20220344333), Jung et al (US 20220344461), Lin et al (US 20210202497), Smith et al (US 10770479), Paul et al (US 10756096), Yang et al (US 20200220006), Lee (US 20190123046), Lee (US 20170194425), Anderson et al (US 9613955), and Kim et al (US 20160343858).
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/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818