Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendments to the specification filed on July 15, 2026 overcome the previous objection.
Response to Arguments
Applicant's arguments filed July 15, 2026 have been fully considered but they are not persuasive. Specifically, applicant argues the claim amendments to claim 1 require that the current confinement layer and light confinement layer are disposed between the active region and the emission side. However, that does not appear to be what the claim amendments require. The amendments state that the current confinement layer and light confinement layer are disposed below a topside of the stack of semiconductor layers and that the current confinement layer forms an exit for light produced by the active region. The phrase “forming an exit for light produced by the active region” it being interpreted as allowing light from the active region to flow through, which is met by layer 15/15A.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 11, 14-20 and 27-28 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the phrase “and below a topside of the stack of semiconductor layers forming an exit for light produced by the active region” and “below the topside of the stack of semiconductor layers” appears to be circular as the previous citation of the stack of semiconductor layers appears to include the planar current confinement layer and the light confinement layer. Thus, it is unclear what additional requirement is needed to meet this limitation as the planar current confinement layer and light confinement layer are part of “the stack of semiconductor layers” and therefore would inherently be below a topside of the stack. In addition, it is not clear if the phrase “forming an exit for light produced by the active region” refers to the planar current confinement layer (this is how it appears in the claim as amended) or the topside of the stack of semiconductor layers. The assumed meaning for examination purposes is that the phrase “forming an exit for light produced by the active region” refers to the planar current confinement layer and that the planar current confinement layer and light confinement layer are part of “the stack of semiconductor layers” and therefore would inherently be below a topside of the stack.
Claims 2-8, 11, 14-20 and 27-28 are rejected since the inherit the indefiniteness of the claims from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11, 14-20 and 27-28 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kuramoto et al US 20190363515, herein after Kuramoto ‘515.
Regarding claims 1 and 28, Kuramoto ‘515 discloses a vertical cavity surface-emitting laser (VCSEL) comprising (VCSEL 10-Figure 1A): a body comprising a vertical stack of semiconductor layers one on top of the other (Figure 1A) , wherein the stack of semiconductor layers comprises: a cavity layer including an active region (14), a planar current confinement layer (15/15A) disposed above the cavity layer (Figure 1A) and below a topside of the stack of semiconductor layers (Figure 1A-since 15/15A are part of the stack of semiconductor layers, this is met) and forming an exit for light produced by the active region (Paragraphs 25 and 34-37, wherein the light exits from the active region 14 and passes through 15/15A to be reflected by mirror 19, thus “forming an exit for light produced by the active region”) the planar current confinement layer (15/15A) including an area of low resistance to current flow (area defined by “D” between 15A) defined by an area of high resistance to current flow (Paragraphs 34-35) , whereupon vertical current flow in the stack of semiconductor layers is directed by the area of high resistance to current flow of the current confinement layer through the area of low resistance to current flow of the current confinement layer (CC-current confinement portion-Figure 1A), and a light confinement layer (LG-light guide layer, 17/18) disposed above the current confinement layer (Shown in Figure 1A) and below the topside of the stack of semiconductor layers (Figure 1A-since light guide layer 12/18 is part of the stack of semiconductor layers, this is met), the light confinement layer including an out-of-plane surface feature, specifically a protrusion in a direction towards the topside of the stack of semiconductor layers (Shown in Figure 1A-protrusion of layer 17) disposed above the area of low resistance to current flow of the current confinement layer (Shown in Figure 1A).
Regarding claim 2, Kuramoto ‘515 further discloses that the stack of semiconductor layers further comprises: a first Distributed Bragg Reflection (DBR) mirror layer (12); disposed below the cavity layer (Figure 1A, wherein 12 is below 14); and a second DBR mirror layer (19) disposed above the light confinement layer (Figure 1A, wherein 19 is above 17/18), and further comprising: first and second electrodes (E1/E2) arranged such that, in response to an electrical bias applied between the first electrical contact (Paragraphs 24-25) and the second DBR mirror layer (19), current flows through the second DBR mirror layer (Paragraphs 39-40 light emission axis CA).
Regarding claim 3, Kuramoto ‘515 further discloses a substrate layer (11) below the stack of semiconductor layers (Figure 1A); wherein the second contact (E1) is disposed on a side of the substrate layer opposite the stack of semiconductor layers, or on a side of the body (E1-wherein this contact is on a side of the body as per Figure 1A), or on the topside of the stack of semiconductor layers, wherein the first contact (E2) is in electrical contact only with the topside of the stack of semiconductor layers (15/16/19 and Paragraphs 33 and 37) and the second contact (E1) is in electrical contact only with the side of the substrate layer (13) opposite the stack of semiconductor layers (Paragraphs 24-25 and 30).
Regarding claims 4 and 16, Kuramoto ‘515 further discloses wherein the area of high resistance to current flow of the current confinement layer (15A) surrounds the area of low resistance to current flow of the current confinement layer (Figure 1A-B).
Regarding claims 5 and 17, Kuramoto ‘515 further discloses that the out-of-plane surface feature of the light confinement layer (17) is positioned in alignment with the area of low resistance (area defined by “D” between 15A) to current flow of the current confinement layer (Figure 1A).
Regarding claims 6 and 18, Kuramoto ‘515 further discloses that the area of low resistance to current flow of the current confinement layer is circular (Paragraph 36).
Regarding claims 7 and 19, Kuramoto ‘515 further discloses that the out-of-plane surface
feature (protrusion 17) of the light confinement layer is coaxial with the circular current confinement layer (Figures 1A-1B).
Regarding claims 8 and 20, Kuramoto ‘515 further discloses that that out-of-plane surface
feature (protrusion 17) of the light confinement layer is round or circular (Figures 1A-1B).
Regarding claims 11 and 27, Kuramoto ‘515 further discloses that the area of high resistance to current flow of the current confinement layer comprises an oxidized or implanted semiconductor layer (Paragraph 34).
Regarding claim 14, Kuramoto ‘515 further discloses an intermediate layer (16) between the current confinement layer (15/15A, CC) and the light confinement layer (17/18 LG layer).
Regarding claim 15, Kuramoto ‘515 further discloses a substrate layer (11) below the stack of semiconductor layers (Figure 1A); a first contact on the topside of the stack of semiconductor layers (E2); and a second contact on a side of the substrate layer opposite the stack of semiconductor layers, or on a side of the body, or on the side of the stack of semiconductor layers opposite the substrate layer (E1), wherein the first contact (E2) is in electrical contact only with the side of the stack of semiconductor layers (15/16/19) opposite the substrate layer (Paragraphs 33 and 37) and the second contact (E1) is in electrical contact only with the side of the substrate layer (13) opposite the stack of semiconductor layers (Paragraphs 24-25 and 30).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSICA S MANNO whose telephone number is (571)272-2339. The examiner can normally be reached Monday-Friday.
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/JESSICA S MANNO/SPE, Art Unit 2898
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