Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species G, Figure 17 in the reply filed on December 18, 2025 is acknowledged.
Claims 9-10, 12-13 and 21-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 18, 2025.
Specification
The disclosure is objected to because of the following informalities: paragraph 40, “the second electrical contact 26” should read “the second electrical contact 25”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11, 14-20 and 27-28 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kuramoto et al US 20190363515, herein after Kuramoto ‘515.
Regarding claims 1 and 28, Kuramoto ‘515 discloses a vertical cavity surface-emitting laser (VCSEL) comprising (VCSEL 10-Figure 1A): a body comprising a vertical stack of semiconductor layers one on top of the other (Figure 1A) , wherein the stack of semiconductor layers comprises: a planar current confinement layer (15/15A) including an area of low resistance to current flow (area defined by “D” between 15A) defined by an area of high resistance to current flow (Paragraphs 34-35) , whereupon vertical current flow in the stack of semiconductor layers is directed by the area of high resistance to current flow of the current confinement layer through the area of low resistance to current flow of the current confinement layer (CC-current confinement portion-Figure 1A); and a light confinement layer (LG-light guide layer, 17/18) disposed above the current confinement layer (Shown in Figure 1A), the light confinement layer including an out-of-plane surface feature, specifically a protrusion (Shown in Figure 1A-protrusion of layer 17) disposed above the area of low resistance to current flow of the current confinement layer (Shown in Figure 1A).
Regarding claim 2, Kuramoto ‘515 further discloses that the stack of semiconductor layers include in order: a first Distributed Bragg Reflection (DBR) mirror layer (12); a cavity layer including an active region (14); the current confinement layer (15/15A): and the light confinement layer (light guide layer 17/18); and a second DBR mirror layer (19) wherein in response to an electrical bias applied between the first DBR mirror layer and the second DBR mirror layer, current flows and light produced by the VCSEL in response to the electrical bias pervades the second DBR mirror layer (Paragraphs 39-40 light emission axis CA).
Regarding claim 14, Kuramoto ‘515 further discloses an intermediate layer (16) between the current confinement layer (15/15A, CC) and the light confinement layer (17/18 LG layer).
Regarding claims 3 and 15, Kuramoto ‘515 further discloses that the stack of semiconductor layers further includes: a substrate layer (11) below the stack of semiconductor layers (Figure 1A); a first contact on a side of the stack of semiconductor layers opposite the substrate layer (E2); and a second contact on a side of the substrate layer opposite the stack of semiconductor layers, or on a side of the body, or on the side of the stack of semiconductor layers opposite the substrate layer (E1), wherein the first contact (E2) is in electrical contact only with the side of the stack of semiconductor layers (15/16/19) opposite the substrate layer (Paragraphs 33 and 37) and the second contact (E1) is in electrical contact only with the side of the substrate layer (13) opposite the stack of semiconductor layers (Paragraphs 24-25 and 30).
Regarding claims 4 and 16, Kuramoto ‘515 further discloses wherein the area of high resistance to current flow of the current confinement layer (15A) surrounds the area of low resistance to current flow of the current confinement layer (Figure 1A-B).
Regarding claims 5 and 17, Kuramoto ‘515 further discloses that the out-of-plane surface feature of the light confinement layer (17) is positioned in alignment with the area of low resistance (area defined by “D” between 15A) to current flow of the current confinement layer (Figure 1A).
Regarding claims 6 and 18, Kuramoto ‘515 further discloses that the area of low resistance to current flow of the current confinement layer is circular shaped (Paragraph 36).
Regarding claims 7 and 19, Kuramoto ‘515 further discloses that the out-of-plane surface
feature (protrusion 17) of the light confinement layer is coaxial with the circular shaped current confinement layer (Figures 1A-1B).
Regarding claims 8 and 20, Kuramoto ‘515 further discloses that that out-of-plane surface
feature (protrusion 17) of the light confinement layer is round or circular-shaped (Figures 1A-1B).
Regarding claims 11 and 27, Kuramoto ‘515 further discloses that the area of high resistance to current flow of the current confinement layer comprises an oxidized or implanted semiconductor layer (Paragraph 34).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited references discloses Vertical Cavity Surface emitting lasers with similar current confinement layers similar to the claims of the instant application.
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/JESSICA S MANNO/SPE, Art Unit 2898
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