DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-7 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paek et al. (PN 9,502,375, of record).
Regarding claim 1, Paek et al. discloses, as shown in Figures 1A and 6, a leadless semiconductor package comprising:
an integrated circuit (IC) die (110) having one or more contacts (111) at an active surface facing a mounting surface of the leadless semiconductor package (bottom surface of 100); and
a plurality of dual-sided stud structures (113,120) providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure (113) extending from a corresponding contact at the active surface to a redistribution layer (a thin portion of 120 at A) and having at least one second conductive pillar structure (120) extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure (120 extends across two 113);
encapsulant material (140) at least partially encapsulating the IC die and the plurality of dual-sided stud structures, wherein the encapsulant material includes:
a first encapsulant layer (upper portion of 140 around 110 and 113) encapsulating the active surface of the IC die and the first pillar structures of the plurality of dual-sided stud structures; and
a second encapsulant layer (lower portion of 140 between and in the 120) encapsulating the second pillar structures of the plurality of dual-sided stud structures and forming a portion of the mounting surface.
Regarding claim 6, Paek discloses the second dimension is at least two times larger than the first dimension (120 extends across two 113).
Regarding claim 7, Paek discloses the second dimension is at least three times larger than the first dimension (120 extends across two 113).
Regarding claim 20, Paek et al. discloses, as shown in Figures 1A and 6, a leadless semiconductor package comprising:
a plurality of first pillar structures (113) extending from contacts (111) at an active surface of an integrated circuit (IC) die (1100;
the IC die and the plurality of first pillar structures in a first encapsulant layer (upper portion of 140 around 110 and 113);
one or more redistribution layers (a thin portion of 120 at A) at a surface of the first encapsulant layer opposite the IC die, the one or more redistribution layers having metallizations electrically and mechanically connected to one or more corresponding first pillar structures of the first plurality of pillar structures;
a plurality of second pillar structures (120) extending from the one or more redistribution layers, each second pillar structure electrically connected to one or more first pillar structures via at least one redistribution layer and having a second dimension in a direction parallel to the active surface that is greater than a corresponding first dimension of each first conductive pillar structure (120 extends across two 113);
the plurality of second pillar structures in a second encapsulant layer (lower portion of 140 between and in the 120); and
the second encapsulant layer and the plurality of second pillar structures are planar to form a mounting surface (bottom surface of 100) for the leadless semiconductor package with exposed surfaces of the plurality of the second pillar structures serving as surface mount pads for the leadless semiconductor package.
Note that the terms “formed in accordance with the method of”, “formed”, “encapsulating”, and “planarizing” are method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, and 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paek et al. (PN 9,502,375, of record) in view of Rivera-Marty (US 2019/0148270, of record).
Regarding claim 4, Paek et al. discloses the claimed invention including the package as explained in the above rejection. Paek et al. does not disclose each second conductive pillar structure comprises a solder wettable flank at an exterior sidewall. However, Rivera-Marty discloses a package having each structure comprises a solder wettable flank (26,126) at an exterior sidewall. Note Figures 1 and 3-4 of Rivera-Marty. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form each structure of Paek et al. having a solder wettable flank at an exterior sidewall, such as taught by Rivera-Marty in order to further improve bond integrity, reliability, and enhance the ability to perform any necessary visual inspections of the bonded surfaces.
Regarding claim 5, Paek et al. and Rivera-Marty disclose the package further comprising solder plating (26,125,126) on exterior surfaces of the second conductive pillar structures that are parallel to the mounting surface and on surfaces of the solder wettable flanks of the second conductive pillar structures.
Regarding claim 8, Paek et al. discloses the claimed invention including the package as explained in the above rejection. Paek et al. does not disclose the leadless semiconductor package of claim 1 mounted on a circuit board. However, Rivera-Marty discloses a package having a leadless semiconductor package (10) of claim 1 mounted on a circuit board (200). Note Figure 2 of Rivera-Marty. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the package of Paek et al. having the leadless semiconductor package mounted on a circuit board, such as taught by Rivera-Marty in order to provide the power/signal from the circuit board to the leadless package to perform the desired function.
Regarding claim 9, Paek et al. discloses, as shown in Figures 1A and 6, a leadless semiconductor package comprising:
a first surface (top) and an opposing second surface (bottom);
an integrated circuit (IC) die (10) disposed adjacent to the first surface; and
a conductive fan-out structure to provide contact fan-out from a plurality of contacts (111) of an active surface of the IC die to the second surface of the leadless semiconductor package, the conductive fan-out structure comprising:
a plurality of thick pillar structures (120), each thick pillar structure extending into the leadless semiconductor package from an edge of the second opposing surface, wherein exposed surfaces of the thick pillar structures serve as surface mounting pads for the leadless semiconductor package; and
a plurality of thin pillar structures (113), each thin pillar structure extending into the leadless semiconductor package from a corresponding contact of the plurality of contacts (111) and electrically connected to at least one thick pillar structure via at least one redistribution layer;
encapsulant material (140) at least partially encapsulating the IC die and the conductive fan-out structure, wherein the encapsulant material includes:
a first encapsulant layer (upper portion of 140 around 110 and 113) encapsulating the active surface of the IC die and the plurality of thin pillar structures; and
a second encapsulant layer (lower portion of 140 between and in the 120) encapsulating the plurality of thick pillar structures and forming a portion of the opposing second surface.
Paek et al. does not disclose the thick pillar structures are at least two times as thick as the thin pillar structures. However, Rivera-Marty discloses a package having the thick pillar structures (120) are at least two times as thick as the thin pillar structures. Note Figures 28 of Rivera-Marty. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the thick pillar structures of Paek et al. being at least two times as thick as the thin pillar structures, such as taught by Rivera-Marty in order have the desired structure.
Further, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 10, Paek et al. and Rivera-Marty disclose each second conductive pillar structure comprises a solder wettable flank (26, 126) formed at an exterior sidewall.
Regarding claim 11, Paek et al. and Rivera-Marty disclose the package further comprising: at least one encapsulant layer (140) encapsulating the plurality of thin pillar structures and the plurality of thick pillar structures.
Regarding claim 12, Paek et al. and Rivera-Marty disclose an electronic device comprising a circuit board (200, Figure 2) having the leadless semiconductor package of claim 9 mounted thereon.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive.
It is argued, at pages 10-11 of the Remarks, that Paek et al. discloses encapsulant 140 is a single layer and not two layers, as claimed. This argument is not convincing because Paek et al. discloses the encapsulant material (140) includes a first encapsulant layer (upper portion of 140 around 110 and 113) and a second encapsulant layer (lower portion of 140 between and in the 120) encapsulating the second pillar structures. The first encapsulant layer and the second encapsulant layer of Paek et al. are formed of the same material and making integral as one encapsulant. Since the claimed invention does not recite the first encapsulant layer and the second encapsulant layer are made of different materials, as a result, the first encapsulant layer and the second encapsulant layer would become one encapsulant. Therefore, Applicant’s claims 1, 9 and 20 do not distinguish over the Paek et al. reference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUNG K VU/ Primary Examiner, Art Unit 2897