DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/30/2025 has been entered.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/30/2025 and 1/07/2026 were filed after the mailing date of the final rejection on 8/26/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous rejection: claims 9 through 27 were rejected.
Current rejection: claims 9 through 27 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 through 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “the first of the wiring layer is exposed” in line 10. However, claim 9 also recites that it “contacts the connection pad” in line 10.
If the first surface of the wiring layer is exposed then it cannot also be contacting, and therefore covered by, the connection pad. Further, figure 7 shows that the surface of the wiring layer (121) in contact with the connection pad (141) is not exposed but rather covered by the connection pad. If the applicant intended for the surface of the wiring layer to comprise an exposed portion (not covered by another body) and a portion in contact with the connection pad, then such an arrangement must be illustrated in the figures.
For the purpose of examination the examiner will interpret “exposed from the first insulating layer” to mean “not covered by the first insulating layer” in order to interpret the claims in light of the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 10, 11, 12, 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713)
Regarding claim 9.
Susuki teaches a printed circuit board (fig 1a:1;[para 0019]) comprising: a first insulating layer (fig 1a:14;[para 0020]); a first wiring layer (fig 1a,1b:11;[para 0025]) embedded in a first surface (fig 1b:14a;[para 0021]) of the first insulating layer (fig 1:14;[para 0025]); a connection pad (fig 1b:12,13;[para 0026]) disposed on the first surface (fig 1b:14a;[para 0021]) of the first insulating layer (fig 1b:14;[para 0020] in a stacking direction; […]wherein the first wiring layer (fig 1a,1b:11;[para 0025]) includes first (fig 1b:11w;[para 0024]) and second (fig 1b:11t;[para 0024]) surfaces opposing each other (fig 1a,1b), the first surface (fig 1b:11w;[para 0024]) of the first wiring layer (fig 1b:11;[para 0025]) is exposed from (interpreted to mean not covered by, see above) the first insulating layer (fig 1a:14;[para 0020]) and contacts the connection pad (fig 1b:12,13;[para 0026]), and the second surface (fig 1b:11t;[para 0024]) of the first wiring layer (fig 1a,1b:11;[para 0025]) is covered by the first insulating layer (fig 1:14;[para 0020]), and wherein a roughness of a surface of the first insulating layer (fig 1:14;[para 0020]) […]is different from a roughness of the first surface (fig 1b:11w:;[para 0024]) of the first wiring layer (fig 1b:11:;[para 0020]).
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Suzuki does not teach a cavity formed in the circuit board.
Na teaches a printed circuit board comprising: a first insulating layer (fig 1:151,120;[para 0092]); a first wiring layer (fig 1:145;[para 0063]) embedded in a first surface of the first insulating layer (fig 1:151,120;[para 0092]) through the first surface thereof;
and a cavity (fig 1:160;[para 0031]) formed in the first insulating layer (fig 1:151,120;[para 0092]); wherein the first wiring layer (fig 1:145;[para 0063,0095]) includes first and second surfaces opposing each other (fig 1), the first surface of the first wiring layer (fig 1:145;[para 0093]) is exposed from the first insulating layer (fig 1:151,120;[para 0092]), and the second surface of the first wiring layer (fig 1:145;[para 0093]) is covered by the first insulating layer (fig 1:151,120;[para 0092]), and wherein a roughness of a surface (fig 2:S2;[para 0122]) of the cavity (fig 1,2:160;[para 0123]) of the first insulating layer (fig 1,151,120;[para 0092]) at a bottom of the cavity (fig 1,2:160;[para 0123]) is different from a roughness of the first surface of the first wiring layer (fig 1,2:145;[para 0122]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a cavity in the board in which to embed the device and thereby reduce the height of the packaged structure
Regarding claim 10, Suzuki in view of Na teaches the printed circuit board of claim 9, further:
Na teaches the roughness of the bottom surface (fig 2:S2;[para 0122]) of the cavity (fig 1:160;[para 0122]) is greater than the roughness of the first surface of the first wiring layer (fig 1,2:145;[para 0122,0123]).
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Regarding claim 11, Suzuki in view of Na teaches the printed circuit board of claim 10, further:
Na teaches a roughness of a side surface (fig 2:s1;[para 0122,0123]) of the cavity (fig 1:160;[para 0122]) is greater than the roughness of the first surface of the first wiring layer (fig 1,2:145;[para 0122,0123]).
Regarding claim 12, Suzuki in view of Na teaches the printed circuit board of claim 11, further:
Na teaches the roughness of the bottom surface (fig 2:S2;[para 0122]) of the cavity (fig 1:160;[para 0122]) is substantially the same as the roughness of the side surface (fig 2:s1;[para 0122]) of the cavity (fig 1:160;[para 0122]).
Regarding claim 13, Suzuki in view of Na teaches the printed circuit board of claim 12, further:
Suzuki teaches a roughness of the first surface (fig 1b:14a;[para 0024]) of the first insulating layer (fig 2b:14;[para 0023]) is greater than the roughness of the first surface (fig 1b:11w;[para 0029]) of the first wiring layer (fig 1b:12;[para 0029]).
Regarding claim 15, Suzuki in view of Na teaches the printed circuit board of claim 9, further:
Suzuki teaches a second wiring layer (fig 1a:15;[para 0037]) disposed on a second surface opposing the first surface of the first insulating layer (fig 1a:14;[para 0032]); a first via layer penetrating through at least a portion of the first insulating layer (fig 1a:14;[para 0020]) to connect the first wiring layer (fig 1a:11;[para 0020]) and the second wiring layer (fig 1a:150020]) to each other; a second insulating layer (fig 1a:16;[para 0038]) disposed on the second surface of the first insulating layer (fig 1a:14;[para 0020]), and embedding the second wiring layer (fig 1a:15;[para 0020]) in a first surface of the second insulating layer (fig 1a:16;[para 0035]); a third wiring layer (fig 1a:17;[para 0020]) disposed on a second surface opposing the first surface of the second insulating layer (fig 1a:16;[para 0038]; and a second via layer penetrating through at least a portion of the second insulating layer (fig 1a:16;[para 0038]) to connect the second wiring layer (fig 1a:16;[para 0038]) and the third wiring layer (fig 1a:17;[para 0039]) to each other (fig 1a;[para 0039]).
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Regarding claim 16, Suzuki in view of Na teaches the printed circuit board of claim 15, further:
Suzuki teaches a solder resist layer (fig 1a:19,18;[para 0021]) disposed on the first surface of the first insulating layer (fig 1a:14;[para 0022]) and the second surface of the second insulating layer (fig 1a:16;[para 0021]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713) as applied to claim 9 and further in view Kaneko (US 2015/0008020)
Regarding claim 14.
Suzuki in view of Na teaches the printed circuit board of claim 9 above.
Suzuki in view of Na does not teach the roughness of the second surface of the wiring layer is greater than the first surface of the wiring.
Kaneko teaches a roughness of a second surface opposing the surface of the first wiring (fig 9e:103;[para 0004]) layer is greater than the roughness of the first surface of the first wiring layer (fig 9e:103;[para 0004]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide roughened wiring surface order to increase the contact area and bond strength between the wiring and the insulating material (Kaneko paragraph 51).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713) as applied to claim 9 and further in view Hsu (US 2016/0172292)
Regarding claim 17.
Suzuki in view of Na teaches elements of the printed circuit board of claim 9 above.
Suzuki in view of Na does not teach a build up insulator layer.
Hsu teaches a build-up insulating layer (fig 1:348;[para 0028]) disposed on the first insulating layer (fig 1:306;[para 0028]), wherein the build-up insulating layer (fig 1:348;[para 0028]) is separated from the first insulating layer (fig 1:306;[para 0028]); a build-up wiring layer (fig 1:346;[para 0026]) disposed on or in the build-up insulating layer (348;[para 0028]); an electronic component (fig 1:300;[para 0025]) disposed between the first insulating layer (fig 1:306;[para 0028]) and the build-up insulating layer (fig 1:348;[para 0028]), and at least partially disposed in the cavity (fig 1:360;[para 0025]); a first connection metal (fig 1:352;[para 0025]) connecting the electronic component (fig 1:300;[para 0025]) and the connection pad (fig 1:316;[para 0025]) to each other (fig 1;[para 0025]); and a second connection metal (fig 1:328;[para 0025]) connecting the connection pad (fig 1:316;[para 0025]) and the build-up wiring layer (fig 1:346;[para 0025]) to each other (fig 1;[para 0024,0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a build up insulating layer with wiring in order to provide additional connections and additional redistribution to additional circuitry thereby enabling more flexibility in the circuit layout and subsequent connections
Claim(s) 18, 19, 21, 22, 23, 24, 25, and 26 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713) in view of Kaneko (US 2015/0008020).
Regarding claim 18.
Suzuki teaches a printed circuit board (fig 1a:1;[para 0019]) comprising: a first insulating layer (fig 1a:14;[para 0022]); a first wiring layer (fig 1a:11;[para 0022]) embedded in a first surface (fig 1a:14a;[para 0023]) of the first insulating layer (fig 1a:14;[para 0026]), a first surface (fig 1a:11w,11v;[para 0024]) of the first wiring layer (fig 1a:11;[para 0022]) being covered by the first insulating layer (fig 1a:14;[para 0022]); a connection pad (fig 1b:12,13;[para 0029]) disposed on the first surface (fig 1b:14a;[para 0023]) of the first insulating layer (fig 1a:14;[para 0023]), and contacting the first wiring layer (fig 1a:11;[para 0026,0033]); a second wiring layer (fig 1a:15;[para 0035]) disposed on a second surface of the first insulating layer (fig 1a:14;[para 0035]); a first via layer connecting the first wiring layer (fig 1a:11;[para 0035]) and the second wiring layer (fig 1a,b:15;[para 0035]) to each other; […] wherein a width of the connection pad (fig 1a,1b:12,13;[para 0029]) is wider than a width of the first wiring layer (fig 1a,1b:11;[para 0022]).
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Suzuki does not teach a cavity in the circuit board.
Na teaches a printed circuit board comprising: a first insulating layer (fig 1:120,151;[para 0095,0097]); a first wiring layer (fig 1,145;[para 0073]) embedded in a first surface of the first insulating layer (fig 1:120,151;[para 0063]); and a cavity (fig 1:160;[para 0097]) formed in the first insulating layer (fig 1:120;[para 0097,0098]) through the first surface thereof such that a surface of the first insulating layer (fig 1:120,151;[para 0063]) forms a bottom of the cavity (fig 1:160;[para 0097]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a cavity in the board in which to embed the device and thereby reduce the height of the packaged structure
Suzuki does not teach the roughness of a surface of the connection pad is less than a roughness of the first surface of the first wiring layer
Kaneko teaches a roughness of a surface of the connection pad (fig 9e:102;[para 0004]) is smaller than a roughness of the first surface of the first wiring layer (fig 9e:103;[para 0004]), and wherein a width of the connection pad (fig 9e:102;[para 0004,0032]) is wider than a width of the first wiring layer (fig 9e:103;[para 0004])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide roughened wiring surface and wider pad area in order to increase the contact area and bond strength between the wiring and the insulating material (Kaneko paragraph 51).
Regarding claim 19, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Suzuki teaches at least a portion of the connection pad (fig 1b:12,13;[para 0026]) is connected to the first surface (fig 1b:14a;[para 0031]) of the first insulating layer (fig 1a,1b:14;[para 0031]).
Regarding claim 21, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Na teaches a depth of the cavity (fig 1:160;[para 0075)) is deeper than a thickness of the first wiring layer (fig 1,2:144;[para 0073]).
Regarding claim 22, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Suzuki teaches a solder resist layer (fig 1a:19;[para 0021]) disposed on the first surface (fig 1a:14a;[para 0021]) of the first insulating layer (fig 1a:14;[para 0021]).
Regarding claim 23, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 22, further:
Suzuki teaches the solder resist layer (fig 1a:19;[para 0021]) comprises a first opening (fig 1b:19x;[para 0028]) exposing at least a portion of the connection pad (fig 1a:12,13;[para 0029] ).
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Na teaches a solder resist layer (fig 1:151;[para 0095]) comprises a first opening exposing at least a portion of the [first wiring layer] (fig 1:145;[para 0093] and a second opening exposing at least a portion of the first insulating layer (fig 1:120;[para 0095]).
Regarding claim 24, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 23, further:
Na teaches a width of the second opening is wider than a width of the cavity (fig 1:160;[para 0097]).
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Regarding claim 25, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Suzuki teaches a [smooth] boundary surface (11w) between the first wiring layer (fig 1b:11(0025]) and the connection pad (fig 1b:12,13;[para 0026].
Na teaches a roughness of a bottom surface (fig 2:S2;[para 0139]) of the cavity (fig 1:160;[para 0139]) is greater than a roughness of a surface [of] the first wiring layer (fig 1:145;[para 0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bottom surface of the cavity to be rough in order to improve the bonding between fill material and the cavity walls.
Regarding claim 26, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Suzuki teaches wherein the second surface opposes the first surface of the first insulating layer (fig 1a:14;[para 0022]), wherein the first via layer penetrates through at least a portion of the first insulating layer (fig 1a:14;[para 0022,0023]), and wherein the printed circuit board (fig 1:1;[para 0022]) further comprises: a second insulating layer (fig 1a:16;[para 0038]) disposed on the second surface of the first insulating layer (fig 1a:14;[para 0038]), and embedding the second wiring layer (fig 1a:15;[para 0035]) in a first surface of the second insulating layer (fig 1a:16;[para 0036]); a third wiring layer (fig 1a:17;[para 0039]) disposed on a second surface opposing the first surface of the second insulating layer (fig 1a:16;[para 0039]); and a second via layer penetrating through at least a portion of the second insulating layer (fig 1a:16;[para 0039]) to connect the second wiring layer (fig 1a:15;[para 0039]) and the third wiring layer (fig 1a:17;[para 0039]) to each other.
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Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713) in view of Kaneko (US 2015/0008020) as applied to claim 18 and further in view of Lee (US 2023/0047621).
Regarding claim 20.
Regarding claim 20, Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18, further:
Suzuki teaches the first surface (fig 1a,1b:11w,11v;[para 0024]) of the first wiring layer (fig 1a:11;[para 0024]) is [nearly] coplanar (D is 2 to 4 microns) with the first surface (fig 1a,1b:14a;[para 0024]) of the first insulating layer (fig 1a,1b:14;[para 0068]).
Suzuki does not teach that the wiring layer is substantially coplanar with the insulating layer in the embodiment.
Lee teaches the first surface of the first wiring layer (fig 2:121;[para 0060]) is substantially coplanar with the first surface of the first insulating layer (fig 2:111;[para 0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the surface of the wiring layer to be substantially coplanar with the surface of the insulation in order to avoid over etching of the wiring layer during the roughening process (Suzuki [para 0024]) which could lead to excessive thinning of the wiring and possible wire opens.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2016/0064319) in view of Na (US 2022/0262713) in view of Kaneko (US 2015/0008020) as applied to claim 18 and further in view of Hsu (US 2016/0172292)
Regarding claim 27.
Suzuki in view of Na in view of Kaneko teaches the printed circuit board of claim 18 above.
Suzuki in view of Na in view of Kaneko does not teach a build up insulator layer.
Hsu teaches a build-up insulating layer (fig 1:348;[para 0028]) disposed on the first insulating layer (fig 1:306;[para 0029]), wherein the build-up insulating layer (fig 1:348;[para 0028]) is separated from the first insulating layer (fig 1:306;[para 0028]); a build-up wiring layer (fig 1:346;[para 0028]) disposed on or in the build-up insulating layer (fig 1:348;[para 0028]); an electronic component (fig 1:300;[para 0025]) disposed between the first insulating layer (fig 1:306;[para 0029]) and the build-up insulating layer (fig 1:348;[para 0028]), and at least partially disposed in the cavity (fig 1:360;[para 0025]); a first connection metal (fig 1:352;[para 0025]) connecting the electronic component (fig 1:300;[para 0025]) and the connection pad (fig 1:316;[para 0025]) to each other; and a second connection metal (fig 1:328;[para 0024]) connecting the connection pad (fig 1:316;[para 0025]) and the build-up wiring layer (fig 1:346;[para 0028]) to each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a build up insulating layer with wiring in order to provide additional connections to additional circuitry.
Response to Arguments
Applicant's arguments filed 7/30/2025 have been fully considered but they are not persuasive.
The applicant argues that the cavity taught by Na does not comprise a bottom formed of the insulating layer.
However, neither the claims nor the specification suggests that the insulating layer cannot be comprised of sublayers, therefore one of ordinary skill in the art could reasonably understand the insulating layer to comprise sublayers (see Na layers 120 and 150 in the rejection above). This interpretation is explicitly suggested in the applicant’s specification (US pgpub 2023/0245989m paragraph 44) which states “An insulating layer 110 may include the first and second insulating layers 111 and 112”, therefore one must reasonably assume that a layer may comprise sublayers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 14, 2026
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