DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
No claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected inventions or species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/21/25.
Response to Arguments
Applicant's arguments filed 9/24/26 with regard to claims 21 and 25 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the argument that Raghunathan does not disclose a plurality of circuit devices embedded in one or more substrate core layers because PIC 105 was used to anticipate one of the circuit devices: The PIC 105 is not needed to be considered a circuit device to anticipate the claim, so PIC 105 was removed as one of the circuit devices in the rejection, making this argument moot. The plurality of active and/or passive circuit devices are 130 and 135.
Regarding the argument that Raghunathan does not disclose a multichip package substrate: The Interposer RDL, PIC, Via Interposer and Switch RDL are all chips or parts of chips so these components together form a multichip package substrate. The active/passive devices are 130 and 135 and claims 21 and 25 do not include the RDL layers so argument pointing to RDL layers are moot.
Regarding the argument that Raghunathan does not disclose circuit devices embedded in ore or more substrate core layers: As seen in Figs. 1a-c, elements 130 and 135 are formed within PIC 105, which reads on the claim limitation. Via interposer 110 is an electrical circuit device, therefore it is an active circuit device. Switch ASIC 1 and 2 (122) are attached to the multichip package (Interposer RDL, PIC, Via Interposer, Switch RDL) as clearly shown in Fig. 1a and the “shadows” of these devices fall on the chips 130 and 135 as seen in the top-down view of Fig. 1c.
Regarding the argument that Raghunathan does not disclose an overhand past a side edge of package substrate to expose an underside edge-coupling interface or face-down overhangs which applicant argues are a part of claims 22 and 23: Raghunathan teaches the photonic integrated circuit device (105) is attached as a face-down photonic integrated circuit device in the plurality of integrated circuit devices (130/135), where the face-down photonic integrated circuit device (105) extends laterally past a side/cutout of the multichip package substrate (past a side of Switch RDL, which forms a "cutout", see Fig. 1a) so that the exposed fiber coupling region (part of 105) is positioned for edge coupling (top edge) attachment to the optical waveguide fiber (part of 140) and the plurality of integrated circuit devices (130, 135) comprises an encapsulated plurality of integrated circuit devices attached to the first redistribution line stack (Switch RDL) of the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL) (C8 L60 - C9 L5). The summary of these claims reads in more than that is there and does not consider reasonable broadest interpretations. As recited above, all of the claim limitations have been met.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 21, 24 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weng et al (US 2021/0223489 A1). Weng teaches:
1/21/25. An integrated circuit package assembly (Figs. 12-16), comprising:
a multichip package substrate (301, 303, 109, 503) comprising a plurality of active and/or passive circuit devices (1001, 1003) embedded in one or more substrate core layers (109) sandwiched between a first redistribution line stack (201) and a second redistribution line stack (401) wherein the plurality of active and/or passive circuit devices (1001, 1003) comprises circuit devices is an integrated circuit die for implementing a digital functionality (P0093);
a plurality of integrated circuit devices (105, 605, 1501) attached to the first redistribution line stack (201) on the multichip package substrate (301, 303, 109, 503); and
an optical waveguide fiber (901) connected to a photonic integrated circuit device (105) that is located in the plurality of integrated circuit devices (105, 605, 1501) (which is part of the multichip package substrate), where the optical waveguide fiber (901) is optically coupled to an exposed fiber coupling region of the photonic integrated circuit device (105) (P0114),
wherein the plurality of active and/or passive circuit (1001, 1003) devices is positioned for alignment with the plurality of integrated circuit (605, 1501) devices such that a first integrated circuit device (605, 1501) from the plurality of integrated circuit (105, 605, 1501) devices has a shadow within which at least one underlying active and/or passive circuit device (1001, 1003) is located (see Fig. 16).
8/24. The integrated circuit package of claim 1, where the plurality of integrated circuit devices (105, 605, 1501) comprises an encapsulated (within 109) plurality of integrated circuit devices (105, 605, 1501) attached to the first redistribution line stack (201) of the multichip package substrate (301, 303, 109, 503).
Claims 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghunathan et al (US 10,872,854 B2). Raghunathan teaches:
21/25. An integrated circuit package assembly (Fig. 1a-c), comprising:
a multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL) comprising a plurality of active and/or passive circuit devices (130, 135) embedded in one or more substrate core layers (part of 105), wherein the plurality of active and/or passive circuit devices (130, 135) comprises an integrated circuit die for implementing a photonic functionality (C4 L63-67, C5 L10-44);
a plurality of integrated circuit devices (122 - Switch ASIC 1, Switch ASIC 2) attached to the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL); and
an optical waveguide fiber (part of 140) connected to a photonic integrated circuit device (105) that is located in the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL), where the optical waveguide fiber (part of 140) is optically coupled to an exposed fiber coupling region (part of 105) of the photonic integrated circuit device (105) (C6 L43-60, C8 L1-33);
wherein the plurality of active and/or passive circuit devices (130, 135) is positioned for alignment with the plurality of integrated circuit devices (122 - Switch ASIC 1/2) such that a first integrated circuit device (either ASIC 1 or 2) from the plurality of integrated circuit devices (122) has a shadow within which at least one underlying active and/or passive circuit device (130, 135) is located (see Fig. 1c, the Switch ASICs overlap all 130/135 in the plan view, C5 L15-21).
22/23. The integrated circuit package of claim 1/21, where the photonic integrated circuit device (105) is attached as a face-down photonic integrated circuit device in the plurality of integrated circuit devices (130/135), where the face-down photonic integrated circuit device (105) extends laterally past a side/cutout of the multichip package substrate (past a side of Switch RDL, which forms a "cutout", see Fig. 1a) so that the exposed fiber coupling region (part of 105) is positioned for edge coupling (top edge) attachment to the optical waveguide fiber (part of 140).
24. The integrated circuit package of claim 1, where the plurality of integrated circuit devices (130, 135) comprises an encapsulated plurality of integrated circuit devices attached to the first redistribution line stack (Switch RDL) of the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL) (C8 L60 - C9 L5).
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
These claims would be allowable over the prior art of record if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the latter, either alone or in combination, does not disclose nor render obvious an integrated circuit package assembly with the claimed multichip package substrate, active/passive circuit devices, IC devices, first and second RDL stacks and optical fiber wherein the photonic integrated circuit device is attached as a face-down photonic integrated circuit device in the plurality of integrated circuit devices, where the face-down photonic integrated circuit device extends laterally past a (cutout or side) region in multichip package substrate so that the exposed fiber coupling region is positioned for edge coupling attachment to the optical waveguide fiber,
in combination with the rest of the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached 9AM-6PM EST M-F.
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/RYAN A LEPISTO/Primary Examiner, Art Unit 2874
