DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
No claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected inventions or species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/21/25.
Response to Arguments
Applicant’s arguments with respect to the rejected claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghunathan et al (US 10,872,854 B2). Raghunathan teaches:
1/21/25. An integrated circuit package assembly (Fig. 1a-c), comprising:
a multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL) comprising a plurality of active and/or passive circuit devices (105, 130, 135) embedded in one or more substrate core layers (105) sandwiched between a first redistribution line stack (Switch RDL) and a second redistribution line stack (Interposer RDL) wherein the plurality of active and/or passive circuit devices (105, 130, 135) comprises an integrated circuit die for implementing a photonic functionality (C4 L63-67, C5 L10-44);
a plurality of integrated circuit devices (122 – Switch ASIC 1, Switch ASIC 2) attached to the first redistribution line stack (Switch RDL) on the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL); and
an optical waveguide fiber (part of 140) connected to a photonic integrated circuit device (105) that is located in the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL), where the optical waveguide fiber (part of 140) is optically coupled to an exposed fiber coupling region (part of 105) of the photonic integrated circuit device (105) (C6 L43-60, C8 L1-33);
wherein the plurality of active and/or passive circuit devices (105, 130, 135) is positioned for alignment with the plurality of integrated circuit devices (122 – Switch ASIC 1/2) such that a first integrated circuit device (either ASIC 1 or 2) from the plurality of integrated circuit devices (122) has a shadow within which at least one underlying active and/or passive circuit device (130, 135) is located (see Fig. 1c, the Switch ASICs overlap all 130/135 in the plan view, C5 L15-21).
5/6/22/23. The integrated circuit package of claim 1/21, where the photonic integrated circuit device (105) is attached as a face-down photonic integrated circuit device in the plurality of integrated circuit devices (105/130/135), where the face-down photonic integrated circuit device (105) extends laterally past a side/cutout of the multichip package substrate (past a side of Switch RDL, which forms a “cutout”, see Fig. 1a) so that the exposed fiber coupling region (part of 105) is positioned for edge coupling (top edge) attachment to the optical waveguide fiber (part of 140).
8/24. The integrated circuit package of claim 1, where the plurality of integrated circuit devices (105, 130, 135) comprises an encapsulated plurality of integrated circuit devices attached to the first redistribution line stack (Switch RDL) of the multichip package substrate (Interposer RDL, PIC, Via Interposer, Switch RDL) (C8 L60 – C9 L5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached 9AM-6PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached at 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN A LEPISTO/Primary Examiner, Art Unit 2874
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