DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
No claims are withdrawn (currently cancelled) from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/21/25.
Drawings
Figures 1a-d and 2-3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the argument concerning some of the drawings being prior art: Applicant states the prior art drawings are descriptions of the evolution of optics and ASIC integration over time. It is unclear how previous evolution and ASIC integration is not prior art since these are prior evolutions of the devices. Applicant does not state these drawings are not prior art at any point. In fact, the drawings appear to come from at least partially from references cited in applicant’s IDSs, which is a listing of prior art.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2022/0367431 A1). Chen teaches:
1. An integrated circuit package assembly (Fig. 1), comprising:
a multichip package substrate (1) (the package substrate can also be considered to be specific layers 80, 20, 25, 52, 44, 54, 60 – which is just simplified at 1) comprising active and/or passive circuit devices (40, 42) embedded in one or more substrate core layers (44, 50) sandwiched between a first redistribution line stack (54) and a second redistribution line stack (52);
a plurality of integrated circuit devices (part of 60, 65; P0024) attached to the first redistribution line stack (54) on the multichip package substrate (1); and
an optical waveguide fiber (part of 70) connected to a photonic integrated circuit device (part of 60) that is located in the plurality of integrated circuit devices (part of 60, 65), where the optical waveguide fiber (70) is optically coupled to an exposed fiber coupling region (part of 60) of the photonic integrated circuit device (part of 60, 65) (P0025).
5/6. The integrated circuit package of claim 1, where the photonic integrated circuit device (part of 60, 65) is attached as a face-down photonic integrated circuit device (see Fig. 1, the connections are at the bottom) in the plurality of integrated circuit devices (part of 60, 65), where the face-down photonic integrated circuit device (60, 65) extends laterally past a side cut-out region (see 60 at 70) of the multichip package substrate (1) so that the exposed fiber coupling region (at 70) is positioned for edge coupling attachment to the optical waveguide fiber (part of 70) (see Fig. 1, the fiber connects to a lateral extension of 60 at a bottom edge).
8. The integrated circuit package of claim 1, where the plurality of integrated circuit devices (part of 60, 65) comprises an encapsulated plurality of integrated circuit devices (lasers, receivers, waveguides, detectors, semiconductor optical amplifiers (SOA), gratings, and other active and passive semiconductor optical devices are all possible devices encapsulated within 60; P0024) attached to the first redistribution line stack (54) of the multichip package substrate (1).
21. An integrated circuit package assembly (Fig. 1), comprising:
a multichip package substrate (1) comprising active and/or passive circuit devices (40, 42) embedded in one or more substrate core layers (44, 50);
a plurality of integrated circuit devices (part of 60, 65) attached to the multichip package substrate (1) (P0024); and
an optical waveguide fiber (part of 70) connected to a photonic integrated circuit device (part of 60, 65) that is located in the multichip package substrate (1), where the optical waveguide fiber (part of 70) is optically coupled to an exposed fiber coupling region (part of 60) of the photonic integrated circuit device (60, 65) (P0025).
22/23. The integrated circuit package of claim 21, where the photonic integrated circuit device (part of 60, 65) is attached as a face-down photonic integrated circuit device (see Fig. 1, the connections are at the bottom) in the plurality of integrated circuit devices (part of 60, 65), where the face-down photonic integrated circuit device (60, 65) extends laterally past a side cut-out region (see 60 at 70) of the multichip package substrate (1) so that the exposed fiber coupling region (at 70) is positioned for edge coupling attachment to the optical waveguide fiber (part of 70) (see Fig. 1, the fiber connects to a lateral extension of 60 at a bottom edge).
24. The integrated circuit package of claim 1, where the plurality of integrated circuit devices (part of 60, 65) comprises an encapsulated plurality of integrated circuit devices (lasers, receivers, waveguides, detectors, semiconductor optical amplifiers (SOA), gratings, and other active and passive semiconductor optical devices are all possible devices encapsulated within 60; P0024) attached to the multichip package substrate (1) (P0024).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references all teach IC packages with fiber coupled to a photonic chip of the package similar to applicant: US 10996412, US 11417698, US 11527419, US 11762155, US 11841541, US 11894354, US 12038599, US 12100697, US 2024/0264369, US 2024/0329339.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached on 8AM-5PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN A LEPISTO/Primary Examiner, Art Unit 2874