Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 5 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 2 patents granted in the last 365 days
Chipletz Inc. is currently managing 5 pending office actions within the Semiconductors, Circuits & Optics technology area. Each of these 5 actions is assigned to a different individual, resulting in 5 distinct examiners for the portfolio. This matching count between actions and examiners indicates a lack of examiner concentration and a broad distribution of the company's pending matters.
The portfolio is also distributed across 5 distinct art units. This suggests that the technical subject matter of the 5 pending applications is varied enough to require review by five different examination groups. The alignment between the number of actions, examiners, and art units shows a fragmented prosecution landscape for the company.
THOMAS, ERIC W is listed as the busiest examiner for the company. This examiner is responsible for 1 pending office action. Since there are 5 pending actions and 5 distinct examiners, every examiner involved in the portfolio currently handles exactly 1 action. This means the busiest examiner holds no more responsibility than any other examiner assigned to the company's filings.
Based on the USPTO statutory response window for each pending office action. 4 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 4 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 1 (20%) |
| §102 only | 1 (20%) |
| Multi-statute (no §101) | 3 (60%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| THOMAS, ERIC W | 1 | 82.5% | -1.9% |
| LIU, XIAOMING | 1 | 86.5% | +10.7% |
| LOHAKARE, PRATIKSHA JAYANT | 1 | 82.3% | +15.3% |
| VARGHESE, ROSHN K | 1 | 67.5% | +20.6% |
| LEPISTO, RYAN A | 1 | 87.7% | +7.8% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18132336 | Co-Packaging Assembly and Method for Attaching Photonic Dies/Modules to Multi-Chip Active/Passive Substrate | LEPISTO, RYAN A | 36d overdue |
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | LOHAKARE, PRATIKSHA JAYANT | 14d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | LIU, XIAOMING | 30d overdue |
| 18429374 | Low-Equivalent-Series-Resistance Capacitors with Solid-State Current Collectors Using Conductive Inks | THOMAS, ERIC W | 76d |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | VARGHESE, ROSHN K | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | LIU, XIAOMING | 30d overdue |
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | LOHAKARE, PRATIKSHA JAYANT | 14d |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | VARGHESE, ROSHN K | — |
| Art Unit | Apps |
|---|---|
| 2847 | 1 |
| 2812 | 1 |
| 2818 | 1 |
| 2896 | 1 |
| 2874 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18429374 | Low-Equivalent-Series-Resistance Capacitors with Solid-State Current Collectors Using Conductive Inks | THOMAS, ERIC W | 2847 | §102§103§112 | Final Rejection | 76d | Pending | Jan 31, 2024 |
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | LIU, XIAOMING | 2812 | §102§103 | Final Rejection | 30d overdue | Pending | Oct 10, 2023 |
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | LOHAKARE, PRATIKSHA JAYANT | 2818 | §103 | Final Rejection | 14d | Pending | Jun 07, 2023 |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | VARGHESE, ROSHN K | 2896 | §102§103§112 | Non-Final OA | — | Pending | Apr 22, 2023 |
| 18132336 | Co-Packaging Assembly and Method for Attaching Photonic Dies/Modules to Multi-Chip Active/Passive Substrate | LEPISTO, RYAN A | 2874 | §102 | Non-Final OA | 36d overdue | Pending | Apr 07, 2023 |
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