DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/20/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Uoya (PG Pub. No. US 2011/0039396 A1) in view of Sakai et al. (PG Pub. no. US 2005/0116323 A1).
Regarding claim 1, Uoya teaches a wafer level chip scale package, comprising:
a bare silicon die (¶¶ 0006, 0029: 102) comprising an active surface (fig. 1: lower surface of 102 comprising pads 108), a rear surface opposite to the active surface (fig. 1: upper surface of 102), and a sidewall surface between the active surface and the rear surface (fig. 1: lateral surface of 102), wherein the bare silicon die comprises a backside corner between the rear surface and the sidewall surface (fig. 1: top corner(s) of 102);
a plurality of pads (¶ 0030: 108) disposed on the active surface (fig. 1: 108 disposed on lower surface of 102);
a plurality of conductive elements (¶ 0029: terminals 105) disposed on the plurality of pads, respectively (fig. 1: 105 disposed on 108); and
an adhesive layer (¶ 0029: 103), wherein the adhesive layer protrudes beyond the sidewall surfaces of the bare silicon die (figs. 1, 6 and 8-9 among others: 103 extends beyond lateral surface(s) of 102), and wherein the adhesive layer extends along the sidewall surface and wraps around the backside corner (fig. 9: 103 extends along lateral surface(s) of 102 and wraps around top corner).
Uoya does not teach to the package further comprising a backside tape adhered to the rear die surface by using the adhesive, wherein the backside tape protrudes beyond the sidewall surfaces of the bare silicon die, wherein the backside tape is not bent around the backside corner and is not in direct contact with the sidewall surfaces of the bare silicon die.
Sakai teaches a semiconductor package (figs. 1A-1B among others) including a backside tape (¶ 0027: plate 4, adhered to a backside of element 2, formed of resin and providing structural support, thereby meeting the broadest reasonable interpretation of ‘backside tape’) adhered to a rear surface of a semiconductor die by using an adhesive (¶ 0047 & fig. 1B: 4 adhered to backside of semiconductor element 2 by binder/adhesive 5), wherein the backside tape protrudes beyond the sidewall surfaces of the bare silicon die, wherein the backside tape is not bent around a backside corner and is not in direct contact with the sidewall surfaces of the bare silicon die (fig. 1B: 4 protrudes beyond sidewall surfaces of 2, and is not bent around a backside corner and is not in direct contact with the sidewall surfaces of 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Uoya with the backside tape of Sakai, as a means to inhibit damage from occurring in the neighborhood of an outer die periphery, enhancing the reliability after mounting (Sakai, ¶ 0068)
Regarding claim 2, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein the bare silicon die is not encapsulated by a molding compound (Uoya, fig. 9: at least a portion of 102 not encapsulated by mold compound).
Regarding claim 3, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein the plurality of pads comprises solder pads or bump pads (Uoya, ¶ 0030: 108 comprises pads contacting solder balls 105).
Regarding claim 4, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein the plurality of conductive elements comprises solder balls, solder bumps, metal bumps, micro-bumps or metal pillars (Uoya, ¶ 0030: 105 comprises solder balls).
Regarding claim 5, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein the adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die by a distance of 5-40 micrometers (Uoya, ¶ 0040: protrusion 122 includes a distance of around 7.5 µm).
Regarding claim 6, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein a height of the adhesive layer on the sidewall surfaces of the bare silicon die is equal to or less than 25 micrometers (Uoya, ¶ 0040 & fig. 9: height of 103 defined by protrusion with dimension of about 7.5 µm).
Regarding claim 7, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein the adhesive layer only partially covers the sidewall surface of the bare silicon die (Uoya, fig. 9: portion 122 of 103 only partially covers lateral surface of 102).
Regarding claim 8, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein an included angle between an end surface of the adhesive layer and the sidewall surface of the bare silicon die is a right angle (Uoya, fig. 9: included angle between an interior end surface of 103 and lateral surface of 102 forms a substantially right angle).
The Examiner has interpretated the term ‘included angle’ to include an interior surface of the claimed adhesive layer, as shown in the annotated figure above. Should the Applicant traverse on the grounds that the included angle is based only on exterior surfaces (as represented in Applicant’s figs. 3-5), the Examiner notes that such an interpretation would result in the limitations of claim 8 (“an included angle…is a right angle“) to be mutually exclusive to those of claims 9 and 10 (“an included angle…is an acute angle”, “an included angle…is an obtuse angle”). In such a case, Applicant should submit evidence or identify such evidence now of record showing the inventions to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
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Regarding claim 9, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein an included angle between an end surface of the adhesive layer and the sidewall surface of the bare silicon die is an acute angle (Uoya, fig. 9: included angle between a bottom end surface of 103 and a covered portion of lateral surface of 102 forms a substantially acute angle).
The Examiner has interpretated the term ‘included angle’ to include an interior surface of the claimed silicon die, as shown in the annotated figure above. Should the Applicant traverse on the grounds that the included angle is based only on exterior surfaces (as represented in Applicant’s figs. 3-5), the Examiner notes that such an interpretation would result in the limitations of claim 9 (“an included angle…is an acute angle“) to be mutually exclusive to those of claims 8 and 10 (“an included angle…is a right angle”, “an included angle…is an obtuse angle”). In such a case, Applicant should submit evidence or identify such evidence now of record showing the inventions to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
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Regarding claim 10, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein an included angle between an end surface of the adhesive layer and the sidewall surface of the bare silicon die is an obtuse angle (Uoya, fig. 9: included angle between a bottom end surface of 103 and an exposed lateral surface of 102 forms a substantially obtuse angle).
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Regarding claim 11, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 1, wherein a sidewall of the adhesive layer is aligned with a sidewall of the backside tape (Sakai, fig. 2D: sidewall of 5 aligned with sidewall of 4).
Regarding claim 12, Uoya in view of Sakai teaches the wafer level chip scale package according to claim 11, wherein the sidewall of the adhesive layer and the sidewall of the backside tape are arranged substantially parallel to a sidewall surface of the bare silicon die (Sakai, fig. 2D: sidewall of 5 and sidewall of 4 substantially parallel to sidewall of 2).
Response to Arguments
Applicant’s arguments filed on 1/20/2026 with respect to claims 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN TURNER/Examiner, Art Unit 2818
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