Office Action Predictor
Last updated: April 15, 2026
Application No. 18/132,440

THREE-DIMENSIONAL MEMORY DEVICE WITH IMPROVED SIGNAL INTERFERENCE

Final Rejection §102
Filed
Apr 10, 2023
Examiner
RAMALLO, GUSTAVO G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fujian Jinhua Integrated Circuit Co., LTD.
OA Round
2 (Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
514 granted / 541 resolved
+27.0% vs TC avg
Minimal +1% lift
Without
With
+1.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
577
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.0%
+11.0% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on September 4, 2025 is being considered by the examiner. Response to Arguments Applicant’s arguments, per page 7, filed October 27, 2025, with respect to the title have been fully considered and are persuasive. The objection of August 26, 2025 has been withdrawn. Applicant’s arguments, per page 7, filed October 27, 2025, with respect to claim 2 have been fully considered and are persuasive. The 112 rejection of August 26, 2025 has been withdrawn. Applicant’s arguments, per page 7, filed October 27, 2025, with respect to claim 1 have been fully considered and are persuasive. The rejection of August 26, 2025 has been withdrawn. Applicant's arguments filed October 27, 2025 have been fully considered but they are not persuasive. Regarding newly added claim 22, applicant asserts that the prior art of record Yang (US 2013/0134492) does not disclose that the storage layer 152 “conformally covers a sidewall of the conductive pillar 142. However, the storage layer of Yang is described as both 151 and 152, where 151 would conformally cover a sidewall of 142 as described in the updated rejection below. Status of the Claims Claims 11-20 are canceled. Claims 21-22 are added. No new matter is introduced. Claims 1-2 are amended. Claims 1-10 and 21-22 are present for examination. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2013/0134492). Claim 22, Yang discloses (Figs. 3D, 3G and 3I) a three-dimensional memory device, comprising: a substrate (101, substrate, Para [0078]); a stack structure (161-168/110, gates/insulating layers, Para [0087], hereinafter “stack”) disposed on the substrate (stack is disposed on 101) and comprising a plurality of alternating conductive layers (161-168) and dielectric layers (110); and a memory string structure (142/151/152, upper channel/first data storage layer/second data storage layer, Para [0101], hereinafter “string”) extending vertically through the stack structure (string extends vertically through stack), and comprising: a conductive pillar (142, upper channel, since current flows between 142 it would be conductive, Para [0091]); and a storage layer (151/152) disposed between the conductive pillar (142) and the stack structure (151/152 laterally between 142 and stack) and surrounding the conductive pillar (151/152 surrounds 142), wherein the storage layer (151/152) comprises a plurality of first protruding portions (152 considered protruding portions) filling first recesses respectively at interfaces between the conductive layers and the dielectric layers (152 fills recesses at interfaces between 161-168 and 110), wherein the storage layer (151/152) conformally covers a sidewall of the conductive pillar (151 conformally covers a sidewall of 143 of 142 which is labeled in Fig. 3D) and directly contacts sidewalls, top surfaces and bottom surfaces of the dielectric layers (as can be seen in Fig. 3G, 152 directly contacts outer sidewalls of 110, top and bottom surfaces of 110). Allowable Subject Matter Claims 1-10 and 21 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Yang (US 2013/0134492), Komori (US 2012/0211820), Jeong (US 2010/0320528), Son (US 2011/0147724), Kim (US 2011/0303970), Yasuda (US 2008/0237688), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim: Regarding Claim 1 (from which claims 2-10 depend), wherein the storage layer comprises a plurality of first protruding portions filling first recesses respectively at interfaces between the conductive layers and the dielectric layers, wherein the conductive layers and the dielectric layers are in direct contact with each other at the interfaces. Regarding Claim 21, the conductive pillar comprise tungsten, the interfacial layers comprise tungsten silicide… Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.G.R/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Apr 10, 2023
Application Filed
Aug 22, 2025
Non-Final Rejection — §102
Oct 27, 2025
Response Filed
Jan 26, 2026
Final Rejection — §102
Mar 31, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12593449
VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING GATE ELECTRODES WITH METAL-DOPED GRAPHENE
2y 5m to grant Granted Mar 31, 2026
Patent 12593450
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2y 5m to grant Granted Mar 31, 2026
Patent 12588201
MEMORY DEVICE WITH INCREASED DENSITY AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+1.3%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allow rate.

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