Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to all pending claims have been considered but are moot because the arguments do not apply to the current grounds of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-24 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sakakibara (US # 20190043830).
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Regarding Claim 17, Sakakibara (US # 20190043830) teaches a memory array comprising:
a conductor tier (108, 112, 38) comprising upper conductor material (doped semiconductor layers 112, 38) directly above and directly electrically coupled to lower conductor material (metallic conductive layer 108), the upper and lower conductor materials comprising different compositions relative one another (see description of materials at [0048, 49, 108]);
laterally-spaced memory blocks ([0102] describes trenches 79 defining the clusters/blocks) individually comprising a vertical stack comprising alternating insulative tiers (132) and conductive tiers (146), channel-material strings (60) of memory cells extending through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material (shown penetrating down to layer 108 in Fig. 17B), the channel material of the channel-material strings being directly electrically coupled to the upper and lower conductor materials of the conductor tier (“direct” electrical connection from 60 is shown to these recited elements 108, 112, and 38); and
intervening material (74 is formed in trenches 79) laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks (see especially top-down view of trench 79 in Fig. 13B).
Regarding Claim 18, Sakakibara teaches the memory array of claim 17 wherein the upper conductor material comprises conductively-doped semiconductive material (doped semiconductor layers 112, 38).
Regarding Claim 19, Sakakibara teaches the memory array of claim 18 wherein the conductively-doped semiconductive material comprises conductively-doped polysilicon ([0049]).
Regarding Claim 20, Sakakibara teaches the memory array of claim 17 wherein the lower conductor material comprises metal material (metallic conductive layer 108; [0048]).
Regarding Claim 21, Sakakibara teaches the memory array of claim 20 wherein the metal material comprises a metal silicide (see [0048]).
Regarding Claim 22, Sakakibara teaches the memory array of claim 21 wherein the upper conductor material comprises conductively-doped semiconductive material and the lower conductor material comprises metal material (see the rejections above, specifically claims 18 and 20).
Regarding Claim 23, Sakakibara teaches the memory array of claim 22 wherein the upper conductor material comprises conductively-doped polysilicon and the lower conductor material comprises a metal silicide (see the rejections above, specifically claims 19 and 21).
Regarding Claim 24, Sakakibara teaches the memory array of claim 7 wherein the metal silicide comprises tungsten silicide ([0048]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara (US # 20190043830) in view of Lee (US # 20220130791).
Regarding Claim 25, Sakakibara teaches the memory array comprising:
a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material, the upper and lower conductor materials comprising different compositions relative one another (essentially the same limitation as claim 17);
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the channel material of the channel-material strings being directly electrically coupled to the upper and lower conductor materials of the conductor tier (essentially the same limitation as claim 17); and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks (essentially the same limitation as claim 17).
Although Sakakibara discloses much of the claimed invention, it does not explicitly teach the memory array comprising dummy pillars extending through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Lee (US # 20220130791) is in the same or analogous field, and it teaches a memory array (see Fig. 1A and corresponding text) comprising dummy pillars (DPL) extending through insulative tiers (IP) and conductive tiers (CP) and through the upper conductor material (surface portion of CSS that interfaces with stack STA) into the lower conductor material (portion of CSS that is deeper than the surface portion of CSS).
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A person having ordinary skill in the art would have recognized that modifying the memory array of Sakakibara with the dummy pillars suggested by Lee would be obvious. Specifically, the modification suggested by Lee would be to employ a memory array comprising dummy pillars extending through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The rationale for this obvious modification is that dummy pillars provide structural support. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of dummy channels/pillars are well known in the art (see MPEP 2144.01).
Regarding Claim 26, Sakakibara teaches the memory array of claim 25 wherein the channel-material strings extend through the upper conductor material into the lower conductor material (“direct” electrical connection from 60 is shown to these recited elements 108, 112, and 38).
Regarding Claim 27, Lee, as applied to claim 25, teaches the memory array of claim 25 wherein the dummy pillars and the channel-material strings are of the same composition and structure in the conductive tiers where the memory cells are located (poly-Si).
Regarding Claim 28, Lee, as applied to claim 25, teaches the memory array of claim 27 wherein a lowest portion of individual of the dummy pillars is of different composition and structure from that of individual of the channel-material strings ([0058] indicates the material “may include” the same material, and vice versa is implied).
Regarding Claim 29, Sakakibara in view of Lee teaches the memory array of claim 28 wherein the different composition comprises polysilicon (Sakakibara teaches III-V compound semiconductor material for the channel; Lee teaches polysilicon for the dummy channel as an option). It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to select different materials since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899