DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an applications filed
in Korea, KR 10-2020-0071704 on June 13, 2022. Receipt is acknowledged of certified copies of papers
required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/26/2026 has been entered.
Response to Amendment
An Amendment filed on 07/26/2026, responding to the Office Action mailed on 03/11/2026, has
been acknowledged and entered into the record. The present Non-Final Rejection is made with all the suggested amendments being fully considered.
Response to Arguments
On page 13 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the asserted motivation of improved adhesion, reduced oxidation, and stress mitigation to replace Chang Chien's conductive wires 110 with Lu's copper (Cu) pillars 22 and protection layer 26 does not arise from, nor is it relevant to, the wire- based architecture of Chang Chien but instead, only arise in the context of Lu's bump-based architecture and do not correspond to any identified problem in Chang Chien's wire-based system. These arguments are fully considered but are not persuasive. The previous rejection was not based upon a replacement of Chang Chien’s wire 110, but rather a modification of the wire 110 of Chang Chien achieved by including the metal layer 26 of Lu covering the sides of the Lu’s pillar 22. As such, even though Chang Chien does not identify any deficiency in its wire 110, a person of ordinary skill would have still been motivated to combine the teachings of Chang Chien and Lu in order to have a metal layer covering the side surface of the wire of Chang Chien according to the teachings of Lu. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025). This point has been clearly established in every motivational statement included at the end of every claim rejection below for further clarity. Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
On pages 13-14 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the proposed substitution is not a simple design choice, but rather a fundamental architectural change and thus, replacing Chang Chien's conductive wires 110 with Lu's copper pillars 22 would require significant structural redesign and would alter the principle of operation of Chang Chien's package. These arguments are fully considered but are not persuasive for the same reasons indicated above. Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
On page 14 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the Office Action appears to rely on different structures in Chang Chien, Lu, and Kim as allegedly corresponding to the claimed "wire" and does not appear to identify one consistent structure corresponding to the claimed "wire". These arguments are fully considered but are not persuasive. The examiner wishes to once again clarify that the secondary references of Lu and Kim are not relied upon to teach the claimed wire, as this limitation is already taught by the primary reference of Chang Chien. Lu is relied upon only to teach the metal layer covering side surface of the core wire while Kim is relied upon only to teach the limitation “a top surface of the wire is exposed from the metal layer”.
On pages 14-15 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that while Independent claim 1 requires that the metal layer contact a side surface of the same "wire” but Lu and Kim are different from each other with respect to the target structure on which the alleged metal layer is formed and thus the previous rejection appears to selectively rely on different target structures in Lu and Kim, and therefore does not seem to provide a proper and consistent combined structure. Applicant further requests that any further action consistently explain which structure of the cited references is regarded as the claimed "wire" and how the metal layer in the identified references contacts the side surface of that same wire. These arguments are fully considered. Further clarification is provided in the rejection below by italicizing the claims limitations not explicitly disclosed in the primary reference but disclosed in the secondary references. To reiterate, the primary reference of Chang Chien is relied upon to teach the claimed wire while Lu is relied upon to teach the metal layer covering side surface of the core wire and Kim is relied upon to teach the limitation “a top surface of the wire is exposed from the metal layer”.
On pages 15-16 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the Office Action selectively extracts isolated elements-Chang Chien's conductive wires 110 and Lu's copper pillars 22 (bump structures) and recombines them in a manner neither taught nor suggested by the references, and thus the rejection is predicated on an improper piecemeal reconstruction of the cited references and fails to provide an articulated reasoning with rational underpinning explaining why a person of ordinary skill in the art would have combined these specific features in the particular manner proposed. These arguments are fully considered but are not persuasive. The rejection does not combine Chang Chien's conductive wires 110 and Lu's copper pillars 22 but rather modifies Chang Chien’s wire to include the metal layer of Lu covering the sides of the Lu’s pillar. As such, a person of ordinary skill would have still been motivated to combine the teachings of Chang Chien and Lu in order to have a metal layer covering the side surface of the wire of Chang Chien according to the teachings of Lu. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025). Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
On page 16 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the there is no reasonable expectation of success in making the proposed modification as substituting Lu's rigid copper pillars 22 for elongated wires 110 would undermine the ability of Chang Chien's system to accommodate vertical separation and alignment tolerances between redistribution substrates 106 and 112 and would necessitate introducing additional structural features and process changes not contemplated by either reference, further underscoring the lack of predictability in the proposed modification. These arguments are fully considered but are not persuasive for the same reasons indicated above (see first paragraph of this section). Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
On page 17 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that the Office Action on page 5 states "combined the teachings of Chang Chien et al. and Lu et al. to have the vertical conductive structures of Lu et al. disposed in the semiconductor package of Chang Chien et al.", suggesting the proposed combination replaces Chang Chien's conductive wires 110 with Lu's copper pillars 22, yet, at the same time, the Office Action continues to rely on those same conductive wires 110 to satisfy other claim recitations such as the first portion W2 and a second portion T2 of Chang Chien's wires 110 recited in Claim 1. Applicant further argues that once Chang Chien's wires 110 are replaced, they cannot then be relied upon to meet additional claim elements. These arguments have been fully considered and addressed in the current rejection. Examiner first wishes to apologize for the oversight and lack of clarity in the previous actions. The above quoted statement has been changed to “combined the teachings of Chang Chien et al. and Lu et al. to have the metal layer of Lu et al. disposed in the semiconductor package of Chang Chien et al." Further, as mentioned earlier reiteratively, the rejection of Claims 1 and 18 are based upon not on the replacement of the wire of Chang Chen but rather on a modification of Chang Chen’s wire to include the electroplated metal layer of Lu covering side surfaces of the wire. As such, the combination of Chang Chien, Lu and Kim teaches all of the limitations of Claims 1 and 18 as outlined in the rejection below. Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
On page 18 of the remarks filed on 07/26/2026, with regards to the rejection of Claims 1, and 18, Applicant argues that while the other cited references (Arifeen and Marro) are relied upon to teach limitations of dependent claims, they still do not cure the deficiencies of Chang Chien, Lu or Kim in that they fail to teach the limitations "wherein the wire includes a first portion, and a second portion disposed at an end of the first portion and having a hemisphere shape," and "wherein a diameter of the hemisphere shape is greater than a width of the first portion," of independent claim 1 and claim 18. These arguments are fully considered but are not persuasive. As discussed earlier and outlined in the rejection below, the primary reference of Chang Chien already teaches these limitations. Therefore, the rejection of Claims 1, 18 and their dependents in view of the cited prior art references is maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary references.
Claims 1, 3 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 20200006290 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1).
Regarding Claim 1, Chang Chien et al. discloses a semiconductor package comprising:
a first redistribution substrate 106 (Fig. 1H: 106, paragraph 0015);
a semiconductor chip 108 on the first redistribution substrate 106 (Fig. 1H: 108, 106, paragraph 0017);
and vertical conductive structures 110’ spaced apart from a side surface of the semiconductor chip 108 (Fig. 1H: 108, 110’, paragraph 0019),
wherein each of the vertical conductive structures 110’ comprises:
a wire (Fig. 1H: 108, 110’, paragraph 0019),
and a metal layer contacting a side surface of the wire,
wherein the metal layer is an electroplated metal layer,
wherein a top surface of the wire is exposed from the metal layer,
wherein the wire 110’ includes a first portion W2 and a second portion T2 disposed at an end of the first portion W2 and having a hemisphere shape, and wherein a diameter of the hemisphere shape is greater than a width of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020).
Lu et al. teaches a semiconductor package comprising the following limitations not disclosed in Chang Chien et al.:
wherein each of the vertical conductive structures 22, 26 comprises a metal layer 26 contacting a side surface of the wire 22 (Fig. 8: 22, 26, paragraph 0018, 0019)
wherein the metal layer 26 is an electroplated metal layer 26 (paragraph 0019)
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the metal layer of Lu et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprises a metal layer contacting a side surface of the wire and wherein the metal layer is an electroplated metal layer. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Kim et al. teaches a semiconductor package comprising the following limitations not disclosed in Chang Chien et al.:
wherein a top surface of the wire 130a is exposed from the metal layer 130b (Fig. 5: 130, 130a, 130b, paragraph 0054).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Chang Chien et al., Lu et al. and Kim et al. in order to have a top surface of the wire be exposed from the metal layer. Doing so would enable the wire to be in direct contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
Regarding Claim 3, Lu et al. teaches the semiconductor package of claim 1, wherein the wire 22 includes at least one of silver, gold, or aluminum (paragraph 0017), and the metal layer 26 includes copper (paragraph 0021).
Regarding Claim 6, the combination of Chang Chien et al. and Lu et al. teaches the semiconductor package of claim 1, wherein the first redistribution substrate 106 comprises an upper pad 106b disposed on a top surface of the first redistribution substrate 106 (as taught by Chang Chien et al. in Fig. 1H: 106b, 106, paragraph 0015), and wherein the metal layer 26 (of Lu et al.) and the upper pad 106b (of Chang Chien et al.) include the same metal material (metal layer 26 of Lu et al. includes copper according to paragraph 0021 of Lu et al. and the upper pad 106b of Chang Chien et al. also includes copper according to paragraph 0015 of Chang Chien et al.).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the wire 22 and the metal layer 26 of Lu et al. will be in contact with the upper pad 106b of Chang Chien et al.
Regarding Claim 7, Chang Chien et al. fails to teach the semiconductor package of claim 1, further comprising a seed pattern, wherein the seed pattern is in contact with a bottom surface of the wire and a bottom surface of the metal layer.
However, Lu et al. teaches a seed pattern 18, wherein the seed pattern 18 is in contact with a bottom surface of the wire 22 and a bottom surface of the metal layer 26 (Fig. 8: 18, 22, 26, paragraph 0003, 0015).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have a seed pattern, wherein the seed pattern is in contact with a bottom surface of the wire and a bottom surface of the metal layer. Doing so would enable the seed pattern to serve as an adhesion promoting layer and/or a diffusion barrier layer, as recognized by Lu et al. paragraph 0003, 0015).
Regarding Claim 8, Chang Chien et al. fails to teach the semiconductor package of claim 1, further comprising a seed pattern, wherein the seed pattern is in contact with a bottom surface of the metal layer and a side surface of a lower portion of the wire and is spaced apart from a bottom surface of the wire.
However, Lu et al. teaches a seed pattern 18, wherein the seed pattern 18 is in contact with a bottom surface of the metal layer 26 and a side surface of a lower portion of the wire 22 (See Fig. 8: 18, 22, 26, paragraph 0003, 0015).
While Lu et al. fails to explicitly teach that the seed pattern 18 is spaced apart from a bottom surface of the wire 26, it does teach that additional layers maybe formed on the seed layer 18 (paragraph 0015).
Therefore, a person of ordinary skill in the art would have recognized that when additional layers are formed on the seed pattern 18, the seed pattern 18 will be spaced apart from a bottom surface of the wire 26.
Regarding Claim 9, Chang Chien et al. teaches the semiconductor package of claim 1, further comprising a molding member 112’ covering a top surface and the side surface of the semiconductor chip 108 (Fig. 1H: 112’, 108, paragraph 0024).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the molding member 112’ of Chang Chien et al. will be contacting a side surface of the metal layer 26 of Lu et al., and the molding member 122’ of Chang Chien et al. will be spaced apart from the wire due to the presence of the metal layer 26 of Lu et al. surrounding the wire.
Regarding Claim 10, Chang Chien et al. teaches the semiconductor package of claim 9, further comprising a second redistribution substrate 114 on the molding member 112’, wherein the first redistribution substrate 106 comprises: a first insulating layer 106a, and a first redistribution pattern 106b in the first insulating layer 106a, wherein the second redistribution substrate 114 comprises: a second insulating layer 114a, and a second redistribution pattern 114b in the second insulating layer 114a, and wherein each of the vertical conductive structures 110’ is connected to the first redistribution pattern 106b and the second redistribution pattern 114b (Fig. 1B: 106, 106a, 106b, Fig. 1G: 114, 114a, 114b, 110’, paragraph 0015, 0030).
Regarding Claim 11, Chang Chien et al. teaches the semiconductor package of claim 1, further comprising a molding member 112’ covering a top surface and the side surface of the semiconductor chip 108 and a side surface of each of the vertical conductive structures 110’, wherein a top surface of each of the vertical conductive structures 110’ is exposed from the molding member 112’ (See Fig. 1H: 112’, 108, paragraph 0024).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 20200006290 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1), as applied to Claim 1 above, further in view of Arifeen et al. (US 20220344295 A1).
Regarding Claim 2, the combination of Chang Chien et al., Lu et al. and Kim et al. fails to teach the semiconductor package of claim 1, wherein bottom surfaces of the wire and the metal layer are coplanar.
However, Arifeen et al. teaches a semiconductor package, wherein bottom surfaces of the wire 229 and the metal layer 228 are coplanar (see Fig. 2B: 222, 229. 228, paragraph 0031, 0032, 0033).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to have combined the teachings of Chang Chien et al., Lu et al., Kim et al. and Arifeen et al. in order to have bottom surfaces of the wire and the metal layer be coplanar. Doing so would enable good contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2020000629 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1), as applied to Claim 1 above, further in view of Marro et al. (J. Electrochem. Soc. 164 D543, 2017).
Lu et al. teaches the semiconductor package of claim 1, wherein the wire 22 includes a first metal material (copper according to paragraph 0017), wherein the metal layer 26 includes a second metal material (copper according to paragraph 0021), wherein the first metal material and the second metal material include the same material (copper).
Lu et al. fails to explicitly teach wherein a grain size and a crystal direction of the first metal material are different from a grain size and a crystal direction of the second metal material.
However, Lu et al. does teach that wire 22 and the metal layer 26 are formed by an electroplating process but the latter is formed from an electrolytic bath containing organic/inorganic additives such as grain-refining agents, wetting agents, brighteners, complexing agents and inhibitors (paragraphs 0017, 0019). Furthermore, Marro et al. teaches that the Cu deposited via electroplating with and without organic additives each have distinct crystal direction and grain size (see abstract and conclusion).
Therefore, a person of ordinary skill in the art, using the combined teachings of Lu et al. and et al. would have recognized that a grain size and a crystal direction of the first metal material will be different from a grain size and a crystal direction of the second metal material due to each growth process having different growth parameters as taught by Lu et al.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2020000629 A1), in view of Lu et al. (US 2011026317 A1).
Regarding Claim 18, Chang Chien et al. teaches a semiconductor package comprising:
a first package 100 (Fig. 1O: 100, paragraph 0039);
and a second package on the first package 200 (Fig. 1O: 200, paragraph 0039),
wherein the first package 100 comprises:
a first redistribution substrate 114 (Fig. 1O: 114, paragraph 0039);
a first semiconductor chip 108 and vertical conductive structures 110’ on the first redistribution substrate 114 (Fig. 1O: 108, 110’, 114, paragraph 0039),
each of the vertical conductive structures 110’ comprising a wire and a metal layer contacting a side surface of the wire (Fig. 1O: 110’, paragraph 0039);
a second redistribution substrate 106 spaced apart from the first redistribution substrate 114 with the first semiconductor chip 108 and the vertical conductive structures 110’ interposed therebetween (Fig. 1O: 106, 108, 110’, 114, paragraph 0039);
and a first molding member 112’ disposed between the first redistribution substrate 114 and the second redistribution substrate 106 and covering a top surface and a side surface of the first semiconductor chip 108 and a side surface of the metal layer (Fig. 1O: 112’, 106, 108, 114, paragraph 0039),
wherein the second package 200 comprises:
a package substrate (one of the plurality of layers 106a of the second redistribution substrate 106 in Fig 1O is interpreted as the package substrate);
a second semiconductor chip 201 on the package substrate (Fig. 1O: 201, paragraph 0039);
and a second molding member 210 covering a top surface of the package substrate and a top surface and a side surface of the second semiconductor chip 201 (Fig. 1O: 210, 201, paragraph 0039),
wherein the metal layer is an electroplated metal layer,
wherein the wire includes: a first portion W2 and a second portion T2 disposed at an end of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020),
wherein the first portion W2 has a line shape of which a width is substantially constant as a height in a first direction (thickness direction) perpendicular to a top surface of the first redistribution substrate increases (Fig. 1G: W2, T2, 110’, paragraph 0020),
and the second portion T2 has a shape of which a width decreases as a height in the first direction (thickness direction) increases (Fig. 1G: W2, T2, 110’, paragraph 0020),
and wherein another end of the first portion is in contact with the second redistribution substrate, and the second portion is in contact with the first redistribution substrate.
Lu et al. teaches a semiconductor package comprising the following limitations not disclosed in Chang Chien et al:
wherein each of the vertical conductive structures 22, 26 comprises a metal layer 26 contacting a side surface of the wire 22 (Fig. 8: 22, 26, paragraph 0018, 0019, abstract)
wherein the metal layer 26 is an electroplated metal layer 26 (paragraph 0019)
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the metal layer of Lu et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprise a metal layer contacting a side surface of the wire, wherein the metal layer is an electroplated metal layer. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the first molding member of Chang Chien et al. would cover a side surface of the metal layer.
Chang Chien et al. fails to explicitly teach wherein another end of the first portion W2 is in contact with the first redistribution substrate 114, and the second portion T2 is in contact with the second redistribution substrate 106 (Fig. 1G: W2, T2, paragraph 0020). That is, the claimed invention differs in that the wire is reversely connected to the first and second redistribution substrates.
However, according to MPEP § 2144.04 (VI) (C), the rearrangement of the wire is an obvious matter of design choice that achieves the same electrical connection without any unexpected results. (see In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice)).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the claimed invention to reverse the wire connection between the first and second redistribution substrates such that another end of the first portion W2 is in contact with the second redistribution substrate 106, and the second portion T2 is in contact with the first redistribution substrate 114.
Regarding Claim 19, Chang Chien et al. teaches wherein a diameter of the second portion T2 is greater than the width of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020).
Regarding Claim 20, Lu et al. teaches wherein the wire 22 includes at least one of silver, gold, or aluminum (paragraph 0017), and the metal layer 26 includes copper (paragraph 0021).
Allowable Subject Matter
Claims 12-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 12, the closest prior art of record Chang Chien et al. (US 2020000629 A1) teaches a semiconductor package comprising:
a first redistribution substrate 106 (Fig. 1H: 106, paragraph 0015);
a semiconductor chip 108 on the first redistribution substrate 106 (Fig. 1H: 108, 106, paragraph 0017);
and vertical conductive structures 110’ spaced apart from a side surface of the semiconductor chip 108, wherein each of the vertical conductive structures 110’ comprises a wire; and a metal layer contacting a side surface of the wire (Fig. 1H: 108, 110’, paragraph 0019),
wherein a level of a top surface of the wire is the same as a level of a top surface of the metal layer,
and wherein a height of the wire is equal to a height of the metal layer.
Chang Chien et al. fails to teaches wherein each of the vertical conductive structures comprises a metal layer contacting a side surface of the wire, wherein a level of a top surface of the wire is the same as a level of a top surface of the metal layer.
Lu et al. (US 2011026317 A1) teaches a semiconductor package comprising vertical conductive structures 22, 26, wherein each of the vertical conductive structures 22, 26 comprises a wire 22 and a metal layer 26 contacting a side surface of the wire 10 (Fig. 8: 22, 26, paragraph 00724, abstract).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the vertical conductive structures of Lu et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprises a metal layer covering a side surface of the wire. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Kim et al. (US 20180090459 A1) teaches a semiconductor package, wherein a top surface of the wire 130a is the same as a level of a top surface of the metal layer 130b (Fig. 5: 130, 130a, 130b, paragraph 0054).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Lu et al. and Kim et al. in order to have a top surface of the wire be the same as a level of a top surface of the metal layer. Doing so would enable the wire to be in direct contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
However, the prior art of regard fails to teaches, suggest or render obvious the claimed limitation, “and wherein a height of the wire is equal to a height of the metal layer”.
Claims 13-17 are allowed due to their dependency on Claim 12.
Claims 21 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 21, Kim et al. teaches the semiconductor package of Claim 1, wherein a top surface of the first portion (i.e., upper portion) of the wire 130a and a top surface of the metal layer 130b are coplanar (Fig. 5: 13a, 13b).
However, the prior art of record fails to explicitly teach, suggest or render obvious the claim limitations, “wherein the metal layer contacts an entire sidewall of the first portion of the wire and at least a portion of the second portion of the wire”.
Note that in Lin et al., the metal layer 26 only covers an upper portion of the wire 22 (Fig. 8: 22, 26), and similarly in Kim et al., the metal layer 130b only covers an upper portion of the wire 130b (Fig. 5: 130, 130a, 130b). Therefore, both Lin and Kim in combination with Chang Chien et al. does not teach, suggest or render obvious the above limitation.
Regarding Claim 22, Kim et al. teaches the semiconductor package of Claim 18, wherein a top surface of the first portion (i.e., upper portion) of the wire 130a and a top surface of the metal layer 130b are coplanar (Fig. 5: 13a, 13b).
However, the prior art of record fails to explicitly teach, suggest or render obvious the claim limitations, “wherein the metal layer contacts an entire sidewall of the first portion of the wire and at least a portion of the second portion of the wire”.
Note that in Lin et al., the metal layer 26 only covers an upper portion of the wire 22 (Fig. 8: 22, 26), and similarly in Kim et al., the metal layer 130b only covers an upper portion of the wire 130b (Fig. 5: 130, 130a, 130b). Therefore, both Lin and Kim in combination with Chang Chien et al. does not teach, suggest or render obvious the above limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is (571)272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 02/26/2025
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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