DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2025 is being considered by the examiner.
Response to Amendment
An amendment filed on 10/31/2025 in response to the Office Action mailed on 08/11/2025 is
being acknowledged and entered into the record. The present Final Rejection is made by taking into
fully consideration all the amendments.
Response to Arguments
On pages 9-10 of the remarks filed on 10/31/2025, with regards to the rejection of amended Claims 1, 12 and 18, Applicant argues that the prior art of record fails to teach or suggest “ a metal layer contacting a side surface of the wire”. This argument is fully considered but is not persuasive. Chang Chien in view of Lu and Kim teaches the above limitation as outlined in the rejection below. i.e., Lu et al. teaches a semiconductor package comprising vertical conductive structures 22, 26, wherein each of the vertical conductive structures 22, 26 comprises a wire 22 and a metal layer 26 contacting a side surface of the wire 10, (see Fig. 8: 22, 26, paragraph 00724, abstract) and Kim et al. teaches a semiconductor package comprising vertical conductive structures 130, wherein each of the vertical conductive structures 130 comprises a wire 130a and a metal layer 130b contacting a side surface of the wire 130a, and wherein a top surface of the wire 130a is exposed from the metal layer 130b (Fig. 5: 130, 130a, 130b, paragraph 0054). Therefore, the rejection of independent Claims 1, 12, and 18 and all dependent claims in view of Chang Chien in view of Lu and Kim is maintained.
On pages 11-12 of the remarks filed on 10/31/2025, applicant argues that Chan Chien, Lu and Kim each disclose different metal structures produced using different manufacturing processes and therefore there is no reasonable expectation of success in combining the above references in the manner proposed which would results in a metal layer contacting a side surface of the wire. This argument is fully considered but is not persuasive. The instant Claims are directed to a product and not a process. According to MPEP § 2113 (I), the patentability of a product does not depend on its method of production and if the product is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). As such, the claimed product is similar to the product of Chang Chien/Lu/Kim regardless of the different manufacturing process as detailed below in the rejection. Therefore, the rejection of all pertinent claims in view of Chang Chien/Lu/Kim is maintained.
On pages 13-14 of the remarks filed on 10/31/2025, applicant argues that combining the teachings of Lu and Kim with Chang Chien would require a modification of the process between Chang Chien's wire bonding and encapsulation, and there is simply no teaching in Chang Chien, Lu, or Kim to support such a modification and thus, one of ordinary skill in the art would not have had a reasonable expectation of success in modifying Chang Chien with either of Lu or Kim to arrive at the claimed invention. Applicant further argues that to import Lu's pillar plating or Kim's lead coating into Chang Chien, one would have to reorder or omit Chang Chien's mandatory Encapsulation Thinning sequence,
which would alter the principle of operation of Chang Chien's process and defeats any reasonable expectation of success in the proposed combination. These arguments are fully considered but are not persuasive. As mentioned earlier, the instant claims are directed to a product and not a process. According to MPEP § 2113 (I), the patentability of a product does not depend on its method of production and if the product is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). As such, the claimed product is similar to the product of Chang Chien/Lu/Kim regardless of the different manufacturing process as detailed below in the rejection. Therefore, the rejection of all pertinent claims in view of Chang Chien/Lu/Kim is maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 20200006290 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1).
Regarding Claim 1, Chang Chien et al. discloses a semiconductor package comprising:
a first redistribution substrate 106 (Fig. 1H: 106, paragraph 0015);
a semiconductor chip 108 on the first redistribution substrate 106 (Fig. 1H: 108, 106, paragraph 0017);
and vertical conductive structures 110’ spaced apart from a side surface of the semiconductor chip 108, wherein each of the vertical conductive structures 110’ comprises a wire (Fig. 1H: 108, 110’, paragraph 0019),
Chang Chien et al. fails to teach wherein each of the vertical conductive structures comprises a metal layer contacting a side surface of the wire, wherein a top surface of the wire is exposed from the metal layer.
However, Lu et al. teaches a semiconductor package comprising vertical conductive structures 22, 26, wherein each of the vertical conductive structures 22, 26 comprises a wire 22 and a metal layer 26 contacting a side surface of the wire 10, except that a top surface of the wire 22 is exposed from the metal layer 26 (Fig. 8: 22, 26, paragraph 00724, abstract).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the vertical conductive structures of Lu et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprises a metal layer contacting a side surface of the wire. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Kim et al. teaches a semiconductor package comprising vertical conductive structures 130, wherein each of the vertical conductive structures 130 comprises a wire 130a and a metal layer 130b contacting a side surface of the wire 130a, and wherein a top surface of the wire 130a is exposed from the metal layer 130b (Fig. 5: 130, 130a, 130b, paragraph 0054).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Lu et al. and Kim et al. in order to have a top surface of the wire be exposed from the metal layer. Doing so would enable the wire to be in direct contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
Regarding Claim 3, Lu et al. teaches the semiconductor package of claim 1, wherein the wire 22 includes at least one of silver, gold, or aluminum (paragraph 0017), and the metal layer 26 includes copper (paragraph 0021).
Regarding Claim 5, Chang Chien et al. teaches the semiconductor package of claim 1, wherein the wire 110’ includes: a first portion W2 and a second portion T2 disposed at an end of the first portion W2 and having a hemisphere shape, and wherein a diameter of the hemisphere shape is greater than a width of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020).
Regarding Claim 6, the combination of Chang Chien et al. and Lu et al. teaches the semiconductor package of claim 1, wherein the first redistribution substrate 106 comprises: an upper pad 106b disposed on a top surface of the first redistribution substrate 106 (as taught by Chang Chien et al. in Fig. 1H: 106b, 106, paragraph 0015), and wherein the metal layer 26 (of Lu et al.) and the upper pad 106b (of Chang Chien et al.) include the same metal material (metal layer 26 of Lu et al. includes copper according to paragraph 0021 of Lu et al. and the upper pad 106b of Chang Chien et al. also includes copper according to paragraph 0015 of Chang Chien et al.).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the wire 22 and the metal layer 26 of Lu et al. will be in contact with the upper pad 106b of Chang Chien et al.
Regarding Claim 7, Chang Chien et al. fails to teach the semiconductor package of claim 1, further comprising a seed pattern, wherein the seed pattern is in contact with a bottom surface of the wire and a bottom surface of the metal layer.
However, Lu et al. teaches a seed pattern 18, wherein the seed pattern 18 is in contact with a bottom surface of the wire 22 and a bottom surface of the metal layer 26 (Fig. 8: 18, 22, 26, paragraph 0003, 0015).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have a seed pattern, wherein the seed pattern is in contact with a bottom surface of the wire and a bottom surface of the metal layer. Doing so would enable the seed pattern to serve as an adhesion promoting layer and/or a diffusion barrier layer, as recognized by Lu et al. paragraph 0003, 0015).
Regarding Claim 8, Chang Chien et al. fails to teach the semiconductor package of claim 1, further comprising a seed pattern, wherein the seed pattern is in contact with a bottom surface of the metal layer and a side surface of a lower portion of the wire and is spaced apart from a bottom surface of the wire.
However, Lu et al. teaches a seed pattern 18, wherein the seed pattern 18 is in contact with a bottom surface of the metal layer 26 and a side surface of a lower portion of the wire 22 (See Fig. 8: 18, 22, 26, paragraph 0003, 0015).
While Lu et al. fails to explicitly teach that the seed pattern 18 is spaced apart from a bottom surface of the wire 26, it does teach that additional layers maybe formed on the seed layer 18 (paragraph 0015).
Therefore, a person of ordinary skill in the art would have recognized that when additional layers are formed on the seed pattern 18, the seed pattern 18 will be spaced apart from a bottom surface of the wire 26.
Regarding Claim 9, Chang Chien et al. teaches the semiconductor package of claim 1, further comprising a molding member 112’ covering a top surface and the side surface of the semiconductor chip 108 (Fig. 1H: 112’, 108, paragraph 0024).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the molding member 112’ of Chang Chien et al. will be contacting a side surface of the metal layer 26 of Lu et al., and the molding member 122’ of Chang Chien et al. will be spaced apart from the wire due to the presence of the metal layer 26 of Lu et al. surrounding the wire.
Regarding Claim 10, Chang Chien et al. teaches the semiconductor package of claim 9, further comprising a second redistribution substrate 114 on the molding member 112’, wherein the first redistribution substrate 106 comprises: a first insulating layer 106a, and a first redistribution pattern 106b in the first insulating layer 106a, wherein the second redistribution substrate 114 comprises: a second insulating layer 114a, and a second redistribution pattern 114b in the second insulating layer 114a, and wherein each of the vertical conductive structures 110’ is connected to the first redistribution pattern 106b and the second redistribution pattern 114b (Fig. 1B: 106, 106a, 106b, Fig. 1G: 114, 114a, 114b, 110’, paragraph 0015, 0030).
Regarding Claim 11, Chang Chien et al. teaches the semiconductor package of claim 1, further comprising a molding member 112’ covering a top surface and the side surface of the semiconductor chip 108 and a side surface of each of the vertical conductive structures 110’, wherein a top surface of each of the vertical conductive structures 110’ is exposed from the molding member 112’ (See Fig. 1H: 112’, 108, paragraph 0024).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 20200006290 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1), as applied to Claim 1 above, further in view of Arifeen et al. (US 20220344295 A1).
Regarding Claim 2, the combination of Chang Chien et al., Lu et al. and Kim et al. fails to teach the semiconductor package of claim 1, wherein bottom surfaces of the wire and the metal layer are coplanar.
However, Arifeen et al. teaches a semiconductor package comprising a vertical conductive structure 222 including a wire 229 and a metal layer 228, wherein bottom surfaces of the wire 229 and the metal layer 228 are coplanar (see Fig. 2B: 222, 229. 228, paragraph 0031, 0032, 0033).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to have combined the teachings of Chang Chien et al., Lu et al., Kim et al. and Arifeen et al. in order to have bottom surfaces of the wire and the metal layer be coplanar. Doing so would enable good contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2020000629 A1), in view of Lu et al. (US 20110260317 A1) and Kim et al. (US 20180090459 A1), as applied to Claim 1 above, further in view of Marro et al. (J. Electrochem. Soc. 164 D543, 2017).
Lu et al. teaches the semiconductor package of claim 1, wherein the wire 22 includes a first metal material (copper according to paragraph 0017), wherein the metal layer 26 includes a second metal material (copper according to paragraph 0021), wherein the first metal material and the second metal material include the same material (copper).
Lu et al. fails to explicitly teach wherein a grain size and a crystal direction of the first metal material are different from a grain size and a crystal direction of the second metal material.
However, Lu et al. does teach that wire 22 and the metal layer 26 are formed by an electroplating process but the latter is formed from an electrolytic bath containing organic/inorganic additives such as grain-refining agents, wetting agents, brighteners, complexing agents and inhibitors (paragraphs 0017, 0019). Furthermore, Marro et al. teaches that the Cu deposited via electroplating with and without organic additives each have distinct crystal direction and grain size (see abstract and conclusion).
Therefore, a person of ordinary skill in the art, using the combined teachings of Lu et al. and et al. would have recognized that a grain size and a crystal direction of the first metal material will be different from a grain size and a crystal direction of the second metal material due to each growth process having different growth parameters as taught by Lu et al.
Claims 12-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2020000629 A1), in view of Lu et al. (US 2011026317 A1) and Kim et al. (US 20180090459 A1).
Regarding Claim 12, Chang Chien et al. teaches a semiconductor package comprising:
a first redistribution substrate 106 (Fig. 1H: 106, paragraph 0015);
a semiconductor chip 108 on the first redistribution substrate 106 (Fig. 1H: 108, 106, paragraph 0017);
and vertical conductive structures 110’ spaced apart from a side surface of the semiconductor chip 108, wherein each of the vertical conductive structures 110’ comprises a wire (Fig. 1H: 108, 110’, paragraph 0019),
Chang Chien et al. fails to teaches wherein each of the vertical conductive structures comprises a metal layer contacting a side surface of the wire, wherein a level of a top surface of the wire is the same as a level of a top surface of the metal layer.
However, Lu et al. teaches a semiconductor package comprising vertical conductive structures 22, 26, wherein each of the vertical conductive structures 22, 26 comprises a wire 22 and a metal layer 26 contacting a side surface of the wire 10 (Fig. 8: 22, 26, paragraph 00724, abstract).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the vertical conductive structures of Lu et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprises a metal layer covering a side surface of the wire. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Kim et al. teaches a semiconductor package comprising vertical conductive structures 130, including a wire 130a and a metal layer 130b, wherein a top surface of the wire 130a is the same as a level of a top surface of the metal layer 130b (Fig. 5: 130, 130a, 130b, paragraph 0054).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Lu et al. and Kim et al. in order to have a top surface of the wire be the same as a level of a top surface of the metal layer. Doing so would enable the wire to be in direct contact with pads/bumps on the redistribution substrates, yielding better electrical connection.
Regarding Claim 13, Chang Chien et al. further teaches:
a second redistribution substrate 114 vertically spaced apart from the first redistribution substrate 106 with the semiconductor chip 108 interposed therebetween (Fig. 1H: 114, 106, 108, paragraph 0039),
wherein the wire 110’ includes: a first portion W2 extending in a line shape and a second portion T2 disposed at an end of the first portion W2 and having a hemisphere shape, wherein the first portion W2 is connected to the second redistribution substrate 114, and the second portion T2 is connected to the first redistribution substrate 106 (Fig. 1G: W2, T2, 110’, paragraph 0020).
Regarding Claim 15, the combination of Chang Chien et al. and Lu et al. teaches wherein the first redistribution substrate 106 comprises an upper pad 106b (as taught by Chang Chien et al. in Fig. 1H: 106b, 106, paragraph 0015), wherein the metal layer 26 (of Lu et al.) and the upper pad 106b (of Chang Chien et al.) include the same metal material (metal layer 26 of Lu et al. includes copper according to paragraph 0021 of Lu et al. and the upper pad 106b of Chang Chien et al. also includes copper according to paragraph 0015 of Chang Chien et al.).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the wire 22 and the metal layer 26 of Lu et al. will be in contact with the upper pad 106b of Chang Chien et al.
Regarding Claim 16, Chang Chien et al. teaches wherein the first redistribution substrate 106 comprises an upper pad 106b (Fig. 1H: 106b, 106, paragraph 0015), but fails to teach a seed pattern, and wherein the wire and the metal layer are spaced apart from the upper pad with the seed pattern interposed therebetween.
However, Lu et. al teaches a seed pattern 18, and wherein the wire 22 and the metal layer 26 are spaced apart from an upper pad 12 with the seed pattern 18 interposed therebetween (Fig. 8: 18, 22, 26, 12, paragraph 0003, 0015).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have a seed pattern, and wherein the wire and the metal layer are spaced apart from the upper pad with the seed pattern interposed therebetween. Doing so would enable the seed pattern to serve as an adhesion promoting layer and/or a diffusion barrier layer, as recognized by Lu et al. paragraph 0003, 0015).
Regarding Claim 17, Chang Chien et al. teaches wherein the first redistribution substrate 106 comprises an upper pad 106b (Fig. 1H: 106b, 106, paragraph 0015), but fails to teach a seed pattern, wherein the metal layer is spaced apart from the upper pad with the seed pattern interposed therebetween, and wherein a lowermost portion of the wire is disposed below an uppermost portion of the seed pattern.
However, Lu et. al teaches a seed pattern 18, and wherein the metal layer 26 are spaced apart from an upper pad 12 with the seed pattern 18 interposed therebetween, and wherein a lowermost portion of the wire 22 is disposed below an uppermost portion of the seed pattern 18. (Fig. 8: 18, 22, 26, 12, paragraph 0003, 0015).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to come up with the claimed invention. Doing so would enable the seed pattern to serve as an adhesion promoting layer and/or a diffusion barrier layer, as recognized by Lu et al. paragraph 0003, 0015).
Regarding Claim 18, Chang Chien et al. teaches a semiconductor package comprising:
a first package 100 (Fig. 1O: 100, paragraph 0039);
and a second package on the first package 200 (Fig. 1O: 200, paragraph 0039),
wherein the first package 100 comprises:
a first redistribution substrate 114 (Fig. 1O: 114, paragraph 0039);
a first semiconductor chip 108 and vertical conductive structures 110’ on the first redistribution substrate 114 (Fig. 1O: 108, 110’, 114, paragraph 0039),
each of the vertical conductive structures 110’ comprising a wire (Fig. 1O: 110’, paragraph 0039);
a second redistribution substrate 106 spaced apart from the first redistribution substrate 114 with the first semiconductor chip 108 and the vertical conductive structures 110’ interposed therebetween (Fig. 1O: 106, 108, 110’, 114, paragraph 0039);
and a first molding member 112’ disposed between the first redistribution substrate 114 and the second redistribution substrate 106 and covering a top surface and a side surface of the first semiconductor chip 108 (Fig. 1O: 112’, 106, 108, 114, paragraph 0039),
wherein the second package 200 comprises:
a package substrate (one of the plurality of layers 106a of the second redistribution substrate 106 in Fig 1O is interpreted as the package substrate);
a second semiconductor chip 201 on the package substrate (Fig. 1O: 201, paragraph 0039);
and a second molding member 210 covering a top surface of the package substrate and a top surface and a side surface of the second semiconductor chip 201 (Fig. 1O: 210, 201, paragraph 0039),
wherein the wire includes: a first portion W2 and a second portion T2 disposed at an end of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020),
wherein the first portion W2 has a line shape of which a width is substantially constant as a height in a first direction (thickness direction) perpendicular to a top surface of the first redistribution substrate increases (Fig. 1G: W2, T2, 110’, paragraph 0020),
and the second portion T2 has a shape of which a width decreases as a height in the first direction (thickness direction) increases (Fig. 1G: W2, T2, 110’, paragraph 0020).
Chang Chien et al. fails to teach or explicitly teach:
each of the vertical conductive structures comprising a metal layer contacting a side surface of the wire;
the first molding member covering a side surface of the metal layer
and wherein another end of the first portion is in contact with the second redistribution substrate, and the second portion is in contact with the first redistribution substrate.
However, Lu et al. teaches a semiconductor package comprising vertical conductive structure 22, 26, wherein each of the vertical conductive structures 22, 26 comprises a wire 22 and a metal layer 26 contacting a side surface of the wire 22 (Fig. 8: 22, 26, paragraph 00724, abstract).
Therefore, a person of ordinary skill in the art would have combined the teachings of Chang Chien et al. and Lu et al. to have the vertical conductive structures of Jin et al. disposed in the semiconductor package of Chang Chien et al. such that each of the vertical conductive structures comprise a metal layer contacting a side surface of the wire. Doing so would prevent oxidation of the metal in the vertical conductive structure, improve adhesion between the vertical conductive structure and the molding material, as well as prohibit stress from concentrating at certain points, as recognized by Lu et al. (paragraph 0025).
Furthermore, a person of ordinary skill in the art would have recognized that when the vertical conductive structures of Lu et al. is disposed in the semiconductor package of Chang Chien et al., the first molding member of Chang Chien et al. would cover a side surface of the metal layer.
Chang Chien et al. does teach wherein another end of the first portion W2 is in contact with the first redistribution substrate 114, and the second portion T2 is in contact with the second redistribution substrate 106 (Fig. 1G: W2, T2, paragraph 0020). That is, the claimed invention differs in that the wire is reversely connected to the first and second redistribution substrates.
However, according to MPEP § 2144.04 (VI) (C), the rearrangement of the wire is an obvious matter of design choice that achieves the same electrical connection without any unexpected results. (see In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice)).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the claimed invention to reverse the wire connection between the first and second redistribution substrates such that another end of the first portion W2 is in contact with the second redistribution substrate 106, and the second portion T2 is in contact with the first redistribution substrate 114.
Regarding Claim 19, Chang Chien et al. teaches wherein a diameter of the second portion T2 is greater than the width of the first portion W2 (Fig. 1G: W2, T2, 110’, paragraph 0020).
Regarding Claim 20, Lu et al. teaches wherein the wire 22 includes at least one of silver, gold, or aluminum (paragraph 0017), and the metal layer 26 includes copper (paragraph 0021).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 14, the prior art of regard fails to teaches the semiconductor package of Claim 12, wherein a height of the wire is equal to a height of the metal layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is (571)272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 02/26/2025
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 7, 2026