DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 12/17/2025, has been entered. The Applicant has amended claims 1 and 11-12. Accordingly, claims 1-20 remain pending in the application.
Applicant’s amendments to the title and claim 11 have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 9/17/ 2025.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2022-0111628, filed on 09/02/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7-8, 11-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tolpygo (Tolpygo et al., 2014, Supercond. Sci. Technol. 27 025016, DOI 10.1088/0953-2048/27/2/025016).
Regarding claim 1, Tolpygo teaches a semiconductor device (superconducting VLSI circuits, Fig. 5, page 3, col. 2, para. 2), comprising:
a logic cell region (see logic cell comprising a Josephson junction JJ in Illustrative Fig. 1, which is an annotated version of Fig. 5) on a substrate (Si substrate, Illustrative Fig. 1);
an interconnection layer (Nb wiring layers, Illustrative Fig. 1) on the logic cell region (logic cell region, Illustrative Fig. 1), the interconnection layer (Nb wiring layers, Illustrative Fig. 1, page 3, Col. 1, para. 1) comprising a plurality of metal layers (Nb layers, Illustrative Fig. 1) stacked in a vertical direction (vertical direction, Illustrative Fig. 1) on the logic cell region (logic cell region, Illustrative Fig. 1); and
a first vertical structure (first vertical structure, Illustrative Fig. 1) in the interconnection layer (Nb wiring layers, Illustrative Fig. 1),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) vertically connects the logic cell region (logic cell region, Illustrative Fig. 1) to an uppermost metal layer (uppermost metal layer, Illustrative Fig. 1: the up and down directions are as indicated in the figure) of the plurality of metal layers (Nb layers, Illustrative Fig. 1),
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wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) comprises a plurality of unit structures (unit structures, Illustrative Fig. 1), the plurality of unit structures (unit structures, Illustrative Fig. 1) overlapping each other (Illustrative Fig. 1),
wherein each of the plurality of unit structures (unit structures, Illustrative Fig. 1) comprises a lower via (lower via, Illustrative Fig. 1), a lower interconnection line (lower interconnection line, Illustrative Fig. 1), an upper via (lower via, Illustrative Fig. 1), and an upper interconnection line (upper interconnection line, Illustrative Fig. 1),
wherein the lower interconnection line (lower interconnection line, Illustrative Fig. 1) and the upper interconnection line (upper interconnection line, Illustrative Fig. 1) of each respective unit structure (each unit structure, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1) cross each other (Illustrative Fig. 1: adjacent top and bottom Nb wires cross each other, see also Fig. 9),
wherein the upper interconnection line (upper interconnection line, Illustrative Fig. 1) of each of the plurality of unit structures (unit structures, Illustrative Fig. 1) comprises a first upper interconnection line (first upper interconnection line, Illustrative Fig. 1),
wherein the upper interconnection line (upper interconnection line, Illustrative Fig. 1) for each of the plurality of unit structures (unit structures, Illustrative Fig. 1) except for an uppermost unit structure (uppermost unit structure in Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1) comprises a second upper interconnection line (second upper interconnection line, Illustrative Fig. 1) adjacent to the first upper interconnection line (first upper interconnection line, Illustrative Fig. 1), and
wherein the first upper interconnection line (first upper interconnection line, Illustrative Fig. 1) of the uppermost unit structure (uppermost unit structure in Illustrative Fig. 1) is offset in a horizontal direction (horizontal direction, Illustrative Fig. 1) with respect to the first upper interconnection lines (first upper interconnection line, Illustrative Fig. 1) of the remaining unit structures (unit structures other than the uppermost unit structure, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1).
Regarding claim 3, Tolpygo teaches the semiconductor device of claim 1, wherein the first upper interconnection lines (first upper interconnection line, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1) vertically overlap each other (Illustrative Fig. 1), and
wherein the second upper interconnection lines (second upper interconnection line, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1) are vertically overlap each other (Illustrative Fig. 1).
Regarding claim 7, Tolpygo teaches the semiconductor device of claim 1, wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) is configured to provide a roundabout path to a current (see the loops formed between lower interconnection lines through lower and upper vias) transmitted through the first vertical structure (first vertical structure, Illustrative Fig. 1).
Regarding claim 8, Tolpygo teaches the semiconductor device of claim 1, wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) is configured to deliver a signal (page 1, col. 2, para. 1: Tolpygo discloses that metal layers are available for circuit integration. Therefore, the metal layers carry signals between circuits.) or power to the logic cell region (logic cell region, Illustrative Fig. 1).
Regarding claim 9, Tolpygo teaches the semiconductor device of claim 1, wherein the logic cell region (logic cell region, Illustrative Fig. 2) is a driver cell (page 1, col. 1, para. 1: Tolpygo teaches that the Josephson junctions in the logic cell region are used for switching, which makes the logic cell region a driver circuit).
Regarding claim 11, Tolpygo teaches a semiconductor device (superconducting VLSI circuits, Fig. 5, page 3, col. 2, para. 2), comprising:
a logic cell region (see logic cell comprising a Josephson junction JJ in Illustrative Fig. 2, which is an annotated version of Fig. 5) on a substrate (Si substrate, Illustrative Fig. 2);
an interconnection layer (Nb wiring layers, Illustrative Fig. 2) on the logic cell region (logic cell region, Illustrative Fig. 2), the interconnection layer (Nb wiring layers, Illustrative Fig. 2) comprising a plurality of metal layers (Nb layers, Illustrative Fig. 2) on the logic cell region (logic cell region, Illustrative Fig. 2); and
a first vertical structure (first vertical structure, Illustrative Fig. 2) and a second vertical structure (second vertical structure, Illustrative Fig. 2) in the interconnection layer (Nb wiring layers, Illustrative Fig. 2),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 2) and the second vertical structure (second vertical structure, Illustrative Fig. 2) vertically connect the logic cell region (logic cell region, Illustrative Fig. 2) to an n-th metal layer (n-th metal layer, Illustrative Fig. 2) in an uppermost metal layer (uppermost metal layer, Illustrative Fig. 2) of the plurality of metal layers (Nb wiring layers, Illustrative Fig. 2), where n is an from 9 to 15 (10 layers, page 3, col. 2, para. 2),
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wherein each of the first vertical structure (first vertical structure, Illustrative Fig. 2) and the second vertical structure (second vertical structure, Illustrative Fig. 2) comprises alternately stacked lower interconnection lines (lower interconnection lines, Illustrative Fig. 2) and upper interconnection lines (upper interconnection lines, Illustrative Fig. 2),
wherein the lower interconnection lines (lower interconnection lines, Illustrative Fig. 2) and the upper interconnection lines (upper interconnection lines, Illustrative Fig. 2) of each respective vertical structure cross each other (Illustrative Fig. 2: adjacent top and bottom Nb wires cross each other, see also Fig. 9),
wherein the upper interconnection lines (upper interconnection lines, Illustrative Fig. 2) of each of the first vertical structure (first vertical structure, Illustrative Fig. 2) and the second vertical structure (second vertical structure, Illustrative Fig. 2) comprise first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 2) and second upper interconnection lines (second upper interconnection lines, Illustrative Fig. 2) adjacent to each other in a first horizontal direction (first horizontal direction, Illustrative Fig. 2),
wherein a first upper interconnection line (top first upper interconnection line, Illustrative Fig. 2) that is located at a highest vertical level (highest towards up direction, Illustrative Fig. 2) among the first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 2) is located at a vertical level (towards up direction, Illustrative Fig. 2) that is higher than a vertical level of a lower interconnection lone (top lower interconnection line, Illustrative Fig. 2) that is located at a highest vertical level among the lower interconnection lines (lower interconnection lines, Illustrative Fig. 2), and
wherein a second upper interconnection line (top second upper interconnection line, Illustrative Fig. 2) that is located at a highest vertical level (highest towards up direction, Illustrative Fig. 2) among the second upper interconnection lines (second upper interconnection lines, Illustrative Fig. 2) is located at a vertical level (towards up direction, Illustrative Fig. 2) that is lower than a vertical level of the lower interconnection line (top lower interconnection line, Illustrative Fig. 2) that is located at the highest vertical level among the lower interconnection lines (lower interconnection lines, Illustrative Fig. 2).
Regarding claim 12, Tolpygo teaches the semiconductor device of claim 11, wherein at least one layer (layer n-1, Illustrative Fig. 2) of the first vertical structure (first vertical structure, Illustrative Fig. 2) is in an (n-1)-th metal layer (Nb layer coinciding with the layer n-1, Illustrative Fig. 2).
Regarding claim 13, Tolpygo teaches the semiconductor device of claim 11, wherein the lower interconnection lines (upper interconnection lines, Illustrative Fig. 2) and the upper interconnection lines (upper interconnection lines, Illustrative Fig. 2) vertically overlap.
Regarding claim 15, teaches the semiconductor device of claim 11, wherein the first vertical structure (first vertical structure, Illustrative Fig. 2) and the second vertical structure (first vertical structure, Illustrative Fig. 2) are configured to deliver a signal (page 1, col. 2, para. 1: Tolpygo discloses that metal layers are available for circuit integration. Therefore, the metal layers carry signals between circuits.) or power to the logic cell region (logic cell region, Illustrative Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tolpygo (Tolpygo et al., 2014, Supercond. Sci. Technol. 27 025016, DOI 10.1088/0953-2048/27/2/025016) as applied to claims 1, 3, 7-9, 11-13, and 15 above, and further in view of Nagasawa (Nagasawa, et al. New Nb multi-layer fabrication process for large-scale SFQ circuits, Physica C: Superconductivity, Volume 469, Issues 15–20, 2009, Pages 1578-1584, ISSN 0921-4534, https://doi.org/10.1016/j.physc.2009.05.219).
Regarding claim 2, while Tolpygo teaches the semiconductor device of claim 1,
Tolpygo does not teach that the interconnection layer further comprises a connection via on the uppermost metal layer of the plurality of metal layers and a large interconnection line on the connection via, the large interconnection line being a largest interconnection line among interconnection lines of the semiconductor device, and
wherein the first upper interconnection line of the uppermost unit structure of the plurality of unit structures vertically overlaps the connection via.
Nagasawa, on the other hand, teaches a high-density superconducting circuit (Figs. 1 and 9-10; page 5, para. 2-3) comprising a logic cell region (active layer including JJ and R, Fig. 1) and a metal interconnection layer (Nb layers M3-M6 as passive transmission line (PTL) layers, Fig. 1; page 2, para. 2), wherein the interconnection layer (Nb layers M2-M6, Fig. 1, ) further comprises a connection via (contact C1, Fig. 1) on the uppermost metal layer (Nb layer M2, Fig. 1: the up and down directions are the same as indicated for Tolpygo’s semiconductor device shown in Illustrative Fig. 1) of the plurality of metal layers (Nb layers M2-M6, Fig. 1) and a large interconnection line (Nb layer M1, Fig. 1) on the connection via (contact C1, Fig. 1), the large interconnection line (Nb layer M1, Fig. 1) being a largest interconnection line (Nb layer M1 and Nb layer M2 are largest among M1-M6, Fig. 1) among interconnection lines (Nb layers M2-M6, Fig. 1) of the semiconductor device (Fig. 1).
Nagasawa further teaches that the Nb layer M1 provides DC power (Fig. 1) and that it is crucial to keep the DC power layer away from the active layer to reduce the influence of magnetic fields due to large bias currents (page 1, col. 2, para. 2). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to provide the DC power to the logic cell region as a large interconnection line above the interconnection layer, as taught by Nagasawa (Fig. 1) and connect it to the lower metal layers through a connection via which will provide the benefit of reducing the influence on magnetic fields during large bias currents. Because the first uppermost connection line of the uppermost unit structure of the plurality of unit structure in the semiconductor device of Tolpygo directly above the active region (Josephson junction, see Illustrative Fig. 1), the combination of Tolpygo and Nagasawa meets all the limitations of claim 2 such that
the interconnection layer further comprises a connection via on the uppermost metal layer of the plurality of metal layers and a large interconnection line on the connection via, the large interconnection line being a largest interconnection line among interconnection lines of the semiconductor device, and
wherein the first upper interconnection line of the uppermost unit structure of the plurality of unit structures vertically overlaps the connection via.
Regarding claim 10, while Tolpygo teaches the semiconductor device of claim 1,
Tolpygo is silent on that the logic cell region comprises a plurality of logic cells, which are two-dimensionally disposed.
Nagasawa, on the other hand, teaches a high-density superconducting circuit (Figs. 1 and 9-10; page 5, para. 2-3) comprising a logic cell region (active layer including JJ and R, Fig. 1) and a metal interconnection layer (Nb layers M2-M7, Fig. 1), wherein the logic cell region (active layer including JJ and R, Fig. 1) comprises a plurality of logic cells (unit cells, Figs. 9-10), which are two-dimensionally disposed (Table 3 and Fig. 10).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the unit cells of the Nagasawa and corresponding metal interconnection layers are analogous to the ones of Tolpygo, as also evidenced by Tolpygo (see para. 1 of the Introduction of Tolpygo), and would be motivated to form the logic cell region of the semiconductor device of Tolpygo as a two-dimensional array of individual logic cells to obtain a device of high density (Tolpygo, Introduction, para. 1).
Thus, the combination of Tolpygo and Nagasawa meets all the limitations of claim 10.
Allowable Subject Matter
Claims 4-6 and 14 are objected to as being dependent upon a rejected base claim (claim 1 for claims 4-6, and claim 11 for claim 14), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, claim 4, disclosing the limitations that “the uppermost metal layer of the plurality of metal layers comprises a connection line connected to the first vertical structure and the second vertical structure “, “the interconnection layer further comprises a large interconnection line on the connection line and a connection via between the connection line and the large interconnection line, the large interconnection line being a largest interconnection line among interconnection lines of the semiconductor device”, will be allowable if these limitations along with other limitations of claim 4 are incorporated with claim 1.
Regarding claim 5, claim 5, disclosing the limitations that “the uppermost metal layer of the plurality of metal layers comprises a connection line connected to the first vertical structure and the second vertical structure“, “the first current path and the second current path are merged in the lower interconnection line of the uppermost unit structure of the plurality of unit structures, forming a first merged current path connected to the large metal layer”, and “the third current path and the fourth current path are merged in the connection line, forming a second merged current path connected to the large metal layer”, will be allowable if these limitations along with other limitations of claim 5 are incorporated with claim 1.
Regarding claim 6, claim 6, disclosing the limitations regarding a transistor structure and overlying interconnection line, will be allowable if these limitations along with other limitations of claim 6 are incorporated with claim 1.
Regarding claim 14, claim 14, disclosing the limitations that “the n-th metal layer comprises a connection line connected to the first vertical structure and the second vertical structure “, “a first current delivered through the first vertical structure is directly conducted to the connection via”, and “a second current delivered through the second vertical structure is conducted to the connection via through the connection line”, will be allowable if these limitations along with other limitations of claim 14 are incorporated with claim 11.
Claim 16-20 are allowed.
Claim 16 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “the first current path and the second current path are merged in an interconnection line of an (n-2)th metal layer, forming a first merged current path connected to the largest metal layer” and “the third current path and the fourth current path are merged in an interconnection line of then-th metal layer, forming a second merged current path connected to the largest metal layer”.
The closest prior art for the invention disclosed in claim 16 is the combination of Ou (US 2019/0080037 A1) and Ku (US 9,977,857 B1). Ou teaches a semiconductor device (layout 620A and its cross-section 620B, Fig. 6A-B, [0057]), comprising:
a logic cell region (fourth cell 612, Fig. 6B, [0057]; [0013]: “The term "cell" used throughout the present disclosure refers to a group of low-level circuit patterns to implement specific functionalities, such as AND, NAND, XOR, or other features.”) on a substrate (see the substrate 210 in Fig. 2; [0027]: the substrate layer includes the cells);
an interconnection layer (second metallization unit 618, Fig. 6B, [0057]) on the logic cell region (fourth cell 612, Fig. 6B), the interconnection layer (second metallization unit 618, Fig. 6B) comprising a plurality of metal layers (see the labeled metal layers M1 to M4 in Illustrative Fig. 3, which is an annotated version of Fig. 6B, [0057]: “four metal layers” corresponding M1-M4, and [0034]: “In some embodiments, more metal layers may be necessary in order to accommodate additional metal lines and metal vias.”) on the logic cell region (logic cell region, Illustrative Fig. 3) and a large metal layer (metal layer M8, Illustrative Fig. 3) on an n-th metal layer (metal layer M4, Illustrative Fig. 3), wherein the large metal layer (metal layer M8, Illustrative Fig. 3) being a largest metal layer (Illustrative Fig. 3: M8 is the largest metal layer) among the plurality of metal layers (metal layers M1-M4, Illustrative Fig. 3) and wherein the large metal layer (metal layer M8, Illustrative Fig. 3) is an uppermost metal layer (see Illustrative Fig. 3, right panel) of the plurality of metal layers (metal layers M1-M4, Illustrative Fig. 3); and
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a first vertical structure (first vertical structure, Illustrative Fig. 3) and a second vertical structure (second vertical structure, Illustrative Fig. 3) in the interconnection layer (comprising second metallization unit 618 and metal layer M5, Illustrative Fig. 3),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 3) and the second vertical structure (second vertical structure, Illustrative Fig. 3) vertically connect the logic cell region (logic cell region, Illustrative Fig. 3) and the large metal layer (metal layer 8, Illustrative Fig. 3),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 3) is configured to provide a first current path (first current path, Illustrative Fig. 3) and a second current path (first current path, Illustrative Fig. 3) which vertically extend from the logic cell region (logic cell region, Illustrative Fig. 3), and
n is an integer from 9 to 15 (Ou does not explicitly disclose that n is an integer from 9 to
15. However, Ou teaches that a greater number of layers can be used in the vertical structures, without actually specifying the numbers of layers ([0034]), as also evidenced by Hou (US 2014/0306341 A1) and Peng (US 2021/0343650 A1), who are also teaching multilayer interconnect structures for logic devices. While Peng shows an interconnect structure with 11 metal layers (within the range of claimed invention) in an embodiment (Fig. 2A, [0070]), Hou discloses that number of metal layers (M1 to Mn, Fig. 2B) in the vertical structure (interconnecting structure 30, Fig. 2B) may be any number ([0037]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the number of metal layers in the vertical structures can be a design choice and determined according to optimization of the manufacturing cost, space requirements and device performance.)
Ou, however, does not teach that
the second vertical structure is configured to provide a third current path and a fourth current path which vertically extend from the logic cell region,
the first current path and the second current path are merged in an interconnection line of an (n-2)-th metal layer, forming a first merged current path connected to the largest metal layer,
the third current path and the fourth current path are merged in an interconnection line of the n-th metal layer, forming a second merged current path connected to the largest metal layer.
Ku, on the other hand, provides a motivation to modify Ou to make the second vertical structure identical the second vertical structure of the current application, to use the vertical structures in a driver/receiver device (Fig. 4, col.5, lines 50-54). Therefore, the combination of Ou and Ku further teaches that
the second vertical structure is configured to provide a third current path and a fourth current path which vertically extend from the logic cell region.
However, no prior art has been identified to modify the semiconductor device of Ou further to obtain the limitations “the first current path and the second current path are merged in the lower interconnection line of the uppermost unit structure of the plurality of unit structures, forming a first merged current path connected to the large metal layer” and “the third current path and the fourth current path are merged in the connection line, forming a second merged current path connected to the large metal layer“. Therefore, claim 16 is allowed.
Claims 17-20 are also allowed, because claim 17-20 inherit the allowable subject matter directly or indirectly from claim 16.
Response to Arguments
It has been acknowledged that the Applicant amended claims 1 and 11-12 per response dated on 12/17/2025.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1 and 11 overcame all claim rejections made previously based on prior art Ou (US 2019/0080037 A1).
However, amended claims 1 and 11 are now rejected under new grounds based on a new prior-art, Tolpygo (Tolpygo et al., 2014, Supercond. Sci. Technol. 27 025016, DOI 10.1088/0953-2048/27/2/025016), in the current office action. Rejections are also made on claims 2-3, 7-13, and 15 based on this new prior-art or its combination with another new prior art, Nagasawa (Nagasawa, et al. New Nb multi-layer fabrication process for large-scale SFQ circuits, Physica C: Superconductivity, Volume 469, Issues 15–20, 2009, Pages 1578-1584, ISSN 0921-4534, doi.org/10.1016/j.physc.2009.05.219). However, no prior art has been identified that can make the inventions disclosed in claims 4-6 and 14 anticipated or obvious. Therefore, claims 4-6 and 14 are objected because they are dependent on a rejected claim. Previously allowed claims 16-20 remain allowed.
For the purpose of compact prosecution, the examiner notes that incorporating some limitations of the objected claims with the independent claims 1 and 11 might render claims 1 and 11 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812