DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/5/2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2022-0111628, filed on 09/02/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant's amendments on 5/5/2026 have been reviewed and entered. Claims 1, 3-5, 11, and 14 have been amended. Claims 1-20 remain for examination.
Claim Objections
Claims 1 and 3 are objected to because of the following informalities:
Regarding claim 1, claim 1 recites on lines 21-25 that “the first upper interconnection line of the uppermost unit structure is offset in a horizontal direction with respect to the first upper interconnection lines of the remaining unit structures of the plurality of unit structures is adjacent to the second upper interconnection line of the uppermost unit structure in the horizontal direction”. The underlined “is” in this sentence is grammatically wrong, and also it is not clear which structure it is referring to. For the purpose of examination, the Examiner considered this sentence to be “the first upper interconnection line of the uppermost unit structure is offset in a horizontal direction with respect to the first upper interconnection lines of the remaining unit structures of the plurality of unit structures and is adjacent to the second upper interconnection line of the uppermost unit structure in the horizontal direction”.
Regarding claim 3, it is recited on lines 1-2 that “the first upper interconnection lines of the plurality of unit structures vertically overlap each other”. However, in claim 1 on which claim 3 depends, it was disclosed that the first upper interconnection line of the uppermost unit structure is offset in a horizontal direction with respect to the upper interconnection lines of the remaining unit structures. The corresponding figure, Fig. 3, illustrates that there is no vertical overlap between the first upper interconnection line of the uppermost unit structure and the upper interconnection lines of the remaining unit structures. Therefore, to explain this feature of the invention more precisely and remove any potential confusion during interpretation, the phrase “the first upper interconnection lines of the plurality of unit structures vertically overlap each other” on lines 1-2 of claim 3 should be rephrased. The Examiner suggests changing it to “the first upper interconnection lines of the plurality of unit structures, except the first upper interconnection line of the uppermost unit structure, vertically overlap each other”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
More specifically, on lines 8-9 of claim 5 it is recited that “the first vertical structure is configured to provide a first current path and a second current path, which are vertically extended from the logic cell region”, and on lines 10-11 it is recited that “the second vertical structure is configured to provide a third current path and a fourth current path, which are vertically extended from the logic cell region”. However, claim 1, on which claim 5 depends, describes the embodiment shown in Fig. 3, which does not have second and fourth current paths. As summarized in the attached interview summary, The Examiner discussed this issue with the Applicant (Attorney Christian LaPense) to determine if the Applicants aimed to disclose another embodiment which the Examiner fails to indentify. The Applicant confirmed that claim 1 targets the embodiment illustrated in Fig. 3, and the above-mentioned limitations of claim 5 conflicts with this embodiment and is not described in any other embodiment in the disclosure. Therefore, claim 5 is rejected under 35. U.S.C. 112(a). For the purpose of examination, the Examiner considered the first and second current paths as a single “first current path” and the third and fourth current paths as a single “third current path”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ku (US 9,977,857 B1).
Regarding claim 1, Ku teaches a semiconductor device (comprising circuit 300 and via pillar 308, Fig. 3; col. 5, lines 21-35), comprising:
a logic cell region (driver 302, Fig. 3; col. 5, lines 50-54; the driver is a logic circuit as the vial pillars are used for minimizing the negative slack (col. 4, lines 19-54; and claim 1) on a substrate (while Ku does not explicitly disclose a substrate, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the driver);
an interconnection layer (via pillar 308, Fig. 3) on the logic cell region (driver 302, Fig. 4; col. 5, lines 21-35: conductive layer M2 is connected to the driver by inserting via pillar on an output pin of a driver (col. 5, lines 26-33) and along a path having negative slack (col. 4, lines 44-46)), the interconnection layer (via pillar 308, Fig. 3) comprising a plurality of metal layers (conductive layers/tracks M2-M6, Fig. 3; tracks are metal layers (col. 7, lines 44-53)) stacked in a vertical direction (vertical direction in Fig. 3) on the logic cell region (driver 302, Fig. 3);
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a first vertical structure (see first vertical structure as labeled in Illustrative Fig. 1, which is an annotated version of Ku’s Fig. 3) in the interconnection layer (via pillar 308, Illustrative Fig. 1); and
a second vertical structure (second vertical structure, Illustrative Fig. 1) adjacent to the first vertical structure (first vertical structure, Illustrative Fig. 1),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) vertically connects the logic cell region (driver 402, Illustrative Fig. 1) to an uppermost metal layer (layer M6, Illustrative Fig. 1, col. 5, lines 31-33) of the plurality of metal layers,
wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) and the second vertical structure (second vertical structure, Illustrative Fig. 1) comprise a plurality of unit structures (unit structures, Illustrative Fig. 1; col. 5, lines 66-67 and col 6 lines 1-2: “… via pillar could have more than two parallel tracks to further reduce resistance, or may have more or fewer layers by way of comparison (with a corresponding effect on resistance)“, and therefore there can be more than two unit structures),
wherein each of the plurality of unit structures (unit structures, Illustrative Fig. 1; col. ) comprises a lower via (lower via, Illustrative Fig. 1: while there is no via in the lowest unit structure in Illustrative Fig. 1, see col. 5, lines 26-33: “To establish the path 306 between the driver 302 and receiver 304, it may be that vias may be required to connect between a layer at which those circuit elements are included, and a routing layer of an integrated circuit. In the example shown, a plurality of conductive layers are illustrated, shown 30 as layers M2-M6. It is assumed, in the embodiment shown, that layer M2 is electrically connected to the driver 302 and receiver 304, with layer M6 acting as a routing layer.”, therefore layer M2 is connected to the output pin of the driver through a via, which is represented by the arrow in Fig. 3 and Illustrative Fig. 1), a lower interconnection line (lower interconnection line, Illustrative Fig. 1), an upper via (upper via, Illustrative Fig. 1), and an upper interconnection line (upper interconnection line, Illustrative Fig. 1),
wherein the lower interconnection line (lower interconnection line, Illustrative Fig. 1) and the upper interconnection line (upper interconnection line, Illustrative Fig. 1) of each respective unit structure of the plurality of unit structures (unit structures, Illustrative Fig. 1) cross each other (see Illustrative Fig. 1),
wherein the upper interconnection line (upper interconnection line, Illustrative Fig. 1) of each of the plurality of unit structures (unit structures, Illustrative Fig. 1) of the first vertical structure (first vertical structure, Illustrative Fig. 1) comprises a first upper interconnection line (first upper interconnection line, Illustrative Fig. 1),
wherein the upper interconnection line (upper interconnection line, Illustrative Fig. 1) of each of the plurality of unit structures (unit structures, Illustrative Fig. 1) of the second vertical structure (second vertical structure, Illustrative Fig. 1) comprises a second upper interconnection line (second upper interconnection line, Illustrative Fig. 1),
wherein the first upper interconnection line (trace M5 of the first vertical structure, Illustrative Fig. 1) of the uppermost unit structure (top unit structure of the first vertical structure, Illustrative Fig. 1) is offset in a horizontal direction (horizontal direction, Illustrative Fig. 1) with respect to the first upper interconnection lines (layer M3 of the first vertical structure, Illustrative Fig. 1) of the remaining unit structures of the plurality of unit structures (unit structures, Illustrative Fig. 1) is adjacent to the second upper interconnection line (trace M5 of the second vertical structure, Illustrative Fig. 1) of the uppermost unit structure (top unit structure of the second vertical structure, Illustrative Fig. 1) in the horizontal direction (horizontal direction, Illustrative Fig. 1),
wherein the uppermost metal layer (layer M6, Illustrative Fig. 1) of the plurality of metal layers (layers M2-M6, Illustrative Fig. 1) comprises a connection line (metal trace M6) connected to the first vertical structure (first vertical structure, Illustrative Fig. 1) and the second vertical structure (second vertical structure, Illustrative Fig. 1), and
wherein the connection line (metal trace M6, Illustrative Fig. 1) vertically (see vertical direction in Illustrative Fig. 1) overlaps the first upper interconnection line of the uppermost unit structure (trace M5 of the first vertical structure, Illustrative Fig. 1) and the second upper interconnection line of the uppermost unit structure (trace M5 of the second vertical structure, Illustrative Fig. 1).
Regarding claim 2, Ku teaches the semiconductor device of claim 1, wherein the interconnection layer (via pillar 308, Illustrative Fig. 1) further comprises a connection via (connection via, Illustrative Fig. 1) on the uppermost metal layer (layer M6, Illustrative Fig. 1) of the plurality of metal layers (layers M2-M6, Illustrative Fig. 1) and a large interconnection line (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) on the connection via (connection via, Illustrative Fig. 1: the extension of trace M6 is on the connection via through trace M6), the large interconnection line (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) being a largest interconnection line (the extension of trace M6 extends to and includes the layer M6 of the receiver 304, Illustrative Fig. 1) among interconnection lines of the semiconductor device (comprising circuit 300 and via pillar 308, Illustrative Fig. 1), and
wherein the first upper interconnection line of the uppermost unit structure (trace M5 of the first vertical structure, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1) vertically (see vertical direction in Illustrative Fig. 1) overlaps the connection via (connection via, Illustrative Fig. 1).
Regarding claim 5, Ku teaches the semiconductor device of claim 1,
wherein the interconnection layer (via pillar 308, Illustrative Fig. 1) further comprises a large metal layer (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) on the uppermost metal layer (layer M6, Illustrative Fig. 1) of the plurality of metal layers (layers M2-M6, Illustrative Fig. 1), the large metal layer (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) being a largest metal (the extension of trace M6 extends to and includes the layer M6 of the receiver 304, and therefore is largest; Illustrative Fig. 1) among the plurality of metal layers (layers M2-M6, Illustrative Fig. 1),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) is configured to provide a first current path (the current path running through the vias to layer M6 in the first vertical structure, Illustrative Fig. 1) (vertical direction, Illustrative Fig. 1) extended from the logic cell region (driver 302, Illustrative Fig. 1),
wherein the second vertical structure (second vertical structure, Illustrative Fig. 1) is configured to provide a third current path (the current path running through the vias to layer M6 in the second vertical structure, Illustrative Fig. 1)) (vertical direction, Illustrative Fig. 1) extended from the logic cell region (driver 302, Illustrative Fig. 1),
wherein the first current path (the current path running through the vias to layer M6 in the first vertical structure, Illustrative Fig. 1) (metal trace M5 in the first vertical structure, Illustrative Fig. 1) of the uppermost unit structure (top unit structure, Illustrative Fig. 1) of the plurality of unit structures (unit structures, Illustrative Fig. 1), forming a first merged current path connected to the large metal layer (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1), and
wherein the third current path (the current path running through the vias to layer M6 in the second vertical structure, Illustrative Fig. 1) the connection line (metal trace M6, Illustrative Fig. 1), forming a second merged current path connected to the large metal layer (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1).
Regarding claim 7, Ku teaches the semiconductor device of claim 1, wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) is configured to provide a roundabout path to a current (see the loops formed between lower interconnection lines through lower and upper vias in Illustrative Fig. 1) transmitted through the first vertical structure (first vertical structure, Illustrative Fig. 1).
Regarding claim 8, Ku teaches the semiconductor device of claim 1, wherein the first vertical structure (first vertical structure, Illustrative Fig. 1) is configured to deliver a signal (Illustrative Fig. 1 and col. 5 lines 20-33: output of the driver 302 is connected to the input of the receiver to deliver driver signal) or power to the logic cell region.
Regarding claim 9, Ku teaches the semiconductor device of claim 1, wherein the logic cell region (driver 302, Illustrative Fig. 1) is a driver cell (col. 5, lines 17-25).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ku (US 9,977,857 B1) as applied to claims 1-2, 5, and 7-9 above, and further in views of Ou (US 2019/0080037 A1).
Regarding claim 3, while Ku teaches the semiconductor device of claim 1,
Ku does not teach that
the first upper interconnection lines (conductive lines L92a and L94a, Fig. 9A, [0056]) of the plurality of unit structures (comprising) vertically overlap each other, and
the second upper interconnection lines of the plurality of unit structures are vertically overlap each other.
Ou, on the other hand, teaches an interconnection layer (second metallization unit 618, see Illustrative Fig. 2 which is an annotated version of Ou’s Fig. 6B, [0057]) wherein
the first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 2) of the plurality of unit structures (unit structures, Illustrative Fig. 2) vertically (vertical direction in Illustrative Fig. 2) overlap each other, and
the second upper interconnection lines (second upper interconnection lines, Illustrative Fig. 2) of the plurality of unit structures (unit structures, Illustrative Fig. 2) are vertically (vertical direction in Illustrative Fig. 2) overlap each other.
Ou discloses that the interconnection layer, as the interconnection layer of Ku, is also a via pillar structure and provides reduced resistance for the conducted signal ([0014)] and reduces time delay ([0034]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who aims to form vertical structures with many unit structures or multiple vertical structures next to each other to further reduce the resistance of the interconnection layer would be motivated to overlap the first interconnection lines and second interconnection lines, as also disclosed by Ou, in the semiconductor device of Ku to reduce the lateral dimension of the interconnection layer to be able to form a device with high density. Thus, the combination of Ku and Ou meets the limitations of claim 3.
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ku (US 9,977,857 B1) as applied to claims 1-2, 5, and 7-9 above, and further in views of Bark (US 2021/0351123 A1).
Regarding claim 6, while Ku teaches the semiconductor device of claim 1,
Ku is silent about the structure of the logic cell region, and therefore does not teach that
the logic cell region comprises: a first active pattern and a second active pattern formed in an upper portion of the substrate and spaced apart from each other in a first direction;
a first channel pattern and a first source/drain pattern on the first active pattern;
a second channel pattern and a second source/drain pattern on the second active pattern;
a gate electrode on the first channel pattern and the second channel pattern;
an interlayer insulating layer provided on the first source/drain pattern, the second source/drain pattern and the gate electrode;
an active contact penetrating the interlayer insulating layer and connected to at least one of the first source/drain pattern and the second source/drain pattern;
a gate contact penetrating the interlayer insulating layer and connected to the gate electrode; and
an interconnection line on the interlayer insulating layer,
wherein the interconnection line is connected to at least one of the active contact and the gate contact, and
wherein the first vertical structure is provided to electrically connect the interconnection line to the uppermost metal layer of the plurality of metal layers.
Bark, on the other hand, teaches a logic cell region (logic cell LC (MOSFET), Figs. 1 and 2A-D, [0025])
wherein the logic cell region (logic cell LC, Figs. 1 and 2A-D) comprises: a first active pattern (first active region PR, Fig. 2C, [0026]) and a second active pattern (second active region NR, Fig. 2C, [0026]) formed in an upper portion of the substrate (substrate 100, Fig. 2B, [0025]) and spaced apart from each other in a first direction (D1 direction, Fig. 2C);
a first channel pattern (first channel pattern CH1, Fig. 2A, [0030]) and a first source/drain pattern (first source/drain pattern SD1, Fig. 2A, [0031]) on the first active pattern (first active region PR, Fig. 2A);
a second channel pattern (second channel pattern CH2, Fig. 2B, [0030]) and a second source/drain pattern (second source/drain pattern SD2, Fig. 2B, [0031]) on the second active pattern (second active region NR, Fig. 2B);
a gate electrode (gate electrode GE, Fig. 2D, [0033]) on the first channel pattern (first channel pattern CH1, Fig. 2D) and the second channel pattern (second channel pattern CH2, Fig. 2D);
an interlayer insulating layer (second interlayer insulating layer 120, Figs. 2C-D, [0042]) provided on the first source/drain pattern (first source/drain pattern SD1, Fig. 2C), the second source/drain pattern (second source/drain pattern SD2, Fig. 2C) and the gate electrode (gate electrode GE, Fig. 2D);
an active contact (active contact AC, Fig. 2C, [0045]) penetrating the interlayer insulating layer (second interlayer insulating layer 120, Fig. 2C) and connected to at least one of the first source/drain pattern (first source/drain pattern SD1, Fig. 2C) and the second source/drain pattern (second source/drain pattern SD2, Fig. 2C);
a gate contact (gate contact GC, Fig. 2D, [0048]) penetrating the interlayer insulating layer (second interlayer insulating layer 120, Fig. 2D) and connected to the gate electrode (gate electrode GE, Fig. 2D); and
an interconnection line (first lower interconnection lines LIL1, Fig. 2C-D) on the interlayer insulating layer (second interlayer insulating layer 120, Fig. 2C-D),
wherein the interconnection line (first lower interconnection lines LIL1, Fig. 2C-D) is connected to at least one of the active contact (active contact AC of source/drain pattern SD1, Fig. 2C) and the gate contact.
Bark further teaches that the first lower interconnection lines LIL1 may be power/source interconnection line (for example, a drain voltage VDD or a source voltage VSS may be applied to the
first lower interconnection line LIL1) ([0051]), and therefore a person of prdinary skill in the art before the effective filing date of the claimed invention would realize that one of the LIL1 lines connected to a source/drain region of a PFET can be used to form a driver circuit by putting a load between the source/drain region of the PFET and the source voltage. Bark also discloses that the MOSFET device taught by Bark has small size and improved electrical characteristics and reliability ([0003]-[0004]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that using the MOSFET of Bark in driver 302 of Ku can enable manufacturing high density logic devices with compact drivers. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the MOSFET device of Bark with the interconnect structure of Ku by electrically connecting the first vertical structure to the interconnection line to the uppermost metal layer of the plurality of metal layers to provide the driver output, which would lead to a logic device with a driver of improved electrical characteristics and reliability (Bark, [0003]-[0004]).
Thus, the combination of Ku and Bark meets all the limitations of claim 6.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ku (US 9,977,857 B1) as applied to claims 1-2, 5, and 7-9 above, and further in views of Ellis (US 2002/0191448 A1).
Regarding claim 10, while Ku teaches the semiconductor device of claim 1,
Ku does not explicitly disclose that the logic cell region comprises a plurality of cells, which are two-dimensionally disposed (even though Ku discloses that the interconnection layer is placed between multiple circuit elements in an integrated circuit (col. 5, lines 17-33).
Ellis, on the other hand, teaches a semiconductor memory (DRAM device 100, Fig. 1, [0003]) including a logic cell region (bitline drivers 125 and wordline drivers 115, Fig. 1, [0003]-[0004]) with precise timing requirements (Fig. 2, [0005]), wherein the logic cell region (bitline drivers 125 and wordline drivers 115, Fig. 1) comprises a plurality of cells (each bitline driver 125 and wordline driver 115 cell, Fig. 1), which are two-dimensionally disposed (see Fig. 1).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who aims to form a memory device would be motivated to use the driver of Ku as wordlines and bitlines and the receiver as the memory cells which would provide benefit of controlling the timing of the driver signals precisely by the interconnection layer of Ku. Thus, the combination of Ku and Ellis leads to a semiconductor device wherein that the logic cell region comprises a plurality of cells, which are two-dimensionally disposed.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4, disclosing the limitations that “the interconnection layer further comprises … a connection via between the connection line and the large interconnection line”, “a first current delivered through the first vertical structure is directly conducted to the connection via”, and “a second current delivered through the second vertical structure is conducted to the connection via through the connection line” , will be allowable if these limitations along with other limitations of claim 4 are incorporated with claim 1.
Regarding the closest prior art, Ku (US 9,977,857 B1) teaches the semiconductor device of claim 1,
wherein the interconnection layer (via pillar 308, Illustrative Fig. 1) further comprises a large interconnection line (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) on the connection line (metal trace M6, Illustrative Fig. 1), the large interconnection line (extension of trace M6 to the via pillar structure above the receiver 304, Illustrative Fig. 1) being a largest interconnection line among interconnection lines (the extension of trace M6 extends to and includes the layer M6 of the receiver 304, and therefore is largest; Illustrative Fig. 1) of the semiconductor device,
Ku, however, fails to teach that
the interconnection layer further comprises a connection via between the connection line and the large interconnection line,
a first current delivered through the first vertical structure is directly conducted to the connection via, and
a second current delivered through the second vertical structure is conducted to the connection via through the connection line.
There has been no prior art identified that can modify Ku further to meet all the limitations of claim 4. Therefore, claim 4 is objected.
Claim 11-20 are allowed, where claims 11 and 16 are independent claims.
Regarding claims 11-15, independent claim 11 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “connection line connected to the second vertical structure” and “the connection line vertically overlaps … the second upper interconnection line that is located at a highest vertical level among the second upper interconnection lines”, when these limitations are accompanied by the remaining limitations of claim 11.
The closest prior art for the invention disclosed in claim 11 is Tolpygo (Tolpygo et al., 2014, Supercond. Sci. Technol. 27 025016, DOI 10.1088/0953-2048/27/2/025016). Tolpygo teaches a semiconductor device (superconducting VLSI circuits, Fig. 5, page 3, col. 2, para. 2), comprising:
a logic cell region (see logic cell comprising a Josephson junction JJ in Illustrative Fig. 3, which is an annotated version of Fig. 5) on a substrate (Si substrate, Illustrative Fig. 3);
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an interconnection layer (Nb wiring layers, Illustrative Fig. 3) on the logic cell region (logic cell region, Illustrative Fig. 3), the interconnection layer (Nb wiring layers, Illustrative Fig. 3) comprising a plurality of metal layers (Nb layers, Illustrative Fig. 3) on the logic cell region (logic cell region, Illustrative Fig. 3); and
a first vertical structure (first vertical structure, Illustrative Fig. 3) and a second vertical structure (second vertical structure, Illustrative Fig. 3) in the interconnection layer (Nb wiring layers, Illustrative Fig. 3),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 3) and the second vertical structure (second vertical structure, Illustrative Fig. 3) vertically connect the logic cell region (logic cell region, Illustrative Fig. 3) to an n-th metal layer (n-th metal layer, Illustrative Fig. 3) in an uppermost metal layer (uppermost metal layer, Illustrative Fig. 3) of the plurality of metal layers (Nb wiring layers, Illustrative Fig. 3), where n is an from 9 to 15 (10 layers, page 3, col. 2, para. 2),
wherein each of the first vertical structure (first vertical structure, Illustrative Fig. 3) and the second vertical structure (second vertical structure, Illustrative Fig. 3) comprises alternately stacked lower interconnection lines (lower interconnection lines, Illustrative Fig. 3) and upper interconnection lines (upper interconnection lines, Illustrative Fig. 3),
wherein the lower interconnection lines (lower interconnection lines, Illustrative Fig. 3) and the upper interconnection lines (upper interconnection lines, Illustrative Fig. 3) of each respective vertical structure cross each other (Illustrative Fig. 3: adjacent top and bottom Nb wires cross each other, see also Fig. 9),
wherein the upper interconnection lines (upper interconnection lines, Illustrative Fig. 3) of each of the first vertical structure (first vertical structure, Illustrative Fig. 3) and the second vertical structure (second vertical structure, Illustrative Fig. 3) comprise first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 3) and second upper interconnection lines (second upper interconnection lines, Illustrative Fig. 3) adjacent to each other in a first horizontal direction (first horizontal direction, Illustrative Fig. 3),
wherein, in the first vertical structure (first vertical structure, Illustrative Fig. 3), a first upper interconnection line (top first upper interconnection line, Illustrative Fig. 3) that is located at a highest vertical level (highest towards up direction, Illustrative Fig. 3) among the first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 3) is located at a vertical level (towards up direction, Illustrative Fig. 3) that is higher than a vertical level of a lower interconnection lone (top lower interconnection line, Illustrative Fig. 3) that is located at a highest vertical level among the lower interconnection lines (lower interconnection lines, Illustrative Fig. 3), and
wherein, in the first vertical structure (first vertical structure, Illustrative Fig. 3), a second upper interconnection line (top second upper interconnection line, Illustrative Fig. 3) that is located at a highest vertical level (highest towards up direction, Illustrative Fig. 3) among the second upper interconnection lines (second upper interconnection lines, Illustrative Fig. 3) is located at a vertical level (towards up direction, Illustrative Fig. 3) that is lower than a vertical level of the lower interconnection line (top lower interconnection line, Illustrative Fig. 3) that is located at the highest vertical level among the lower interconnection lines (lower interconnection lines, Illustrative Fig. 3),
wherein the uppermost metal layer (uppermost metal layer, Illustrative Fig. 3) of the plurality of metal layers (Nb wiring layers, Illustrative Fig. 3) comprises a connection line (connection line, Illustrative Fig. 3) connected to the first vertical structure (first vertical structure, Illustrative Fig. 3), and
wherein the connection line (connection line, Illustrative Fig. 3) vertically (vertical direction, Illustrative Fig. 3) overlaps the first upper interconnection line (top first upper interconnection line, Illustrative Fig. 3) that is located at a highest vertical level among the first upper interconnection lines (first upper interconnection lines, Illustrative Fig. 3).
Tolpygo, however, fails to teach that
the connection line is connected to the second vertical structure, and
the connection line vertically overlaps the second upper interconnection line that is located at a highest vertical level among the second upper interconnection lines.
No prior art has been identified that can modify the semiconductor device of Tolpygo further to meet the limitations that “connection line connected to the second vertical structure” and “the connection line vertically overlaps … the second upper interconnection line that is located at a highest vertical level among the second upper interconnection lines“. Therefore, claim 11 is allowed.
Claims 12-15 are also allowed, because these claims inherit allowable subject matter from claim 16.
Regarding claims 16-20, independent claim 16 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “the first current path and the second current path are merged in an interconnection line of an (n-2)th metal layer, forming a first merged current path connected to the largest metal layer” and “the third current path and the fourth current path are merged in an interconnection line of the n-th metal layer, forming a second merged current path connected to the largest metal layer”, when these limitations are accompanied by the remaining limitations of claim 16.
The closest prior art for the invention disclosed in claim 16 is the combination of Ou (US 2019/0080037 A1) and Ku (US 9,977,857 B1). Ou teaches a semiconductor device (layout 620A and its cross-section 620B, Fig. 6A-B, [0057]), comprising:
a logic cell region (fourth cell 612, Fig. 6B, [0057]; [0013]: “The term "cell" used throughout the present disclosure refers to a group of low-level circuit patterns to implement specific functionalities, such as AND, NAND, XOR, or other features.”) on a substrate (see the substrate 210 in Fig. 2; [0027]: the substrate layer includes the cells);
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an interconnection layer (second metallization unit 618, Fig. 6B, [0057]) on the logic cell region (fourth cell 612, Fig. 6B), the interconnection layer (second metallization unit 618, Fig. 6B) comprising a plurality of metal layers (see the labeled metal layers M1 to M4 in Illustrative Fig. 4, which is an annotated version of Fig. 6B, [0057]: “four metal layers” corresponding M1-M4, and [0034]: “In some embodiments, more metal layers may be necessary in order to accommodate additional metal lines and metal vias.”) on the logic cell region (logic cell region, Illustrative Fig. 4) and a large metal layer (metal layer M8, Illustrative Fig. 4) on an n-th metal layer (metal layer M4, Illustrative Fig. 4), wherein the large metal layer (metal layer M8, Illustrative Fig. 4) being a largest metal layer (Illustrative Fig. 4: M8 is the largest metal layer) among the plurality of metal layers (metal layers M1-M4, Illustrative Fig. 4) and wherein the large metal layer (metal layer M8, Illustrative Fig. 4) is an uppermost metal layer (see Illustrative Fig. 4, right panel) of the plurality of metal layers (metal layers M1-M4, Illustrative Fig. 4); and
a first vertical structure (first vertical structure, Illustrative Fig. 4) and a second vertical structure (second vertical structure, Illustrative Fig. 4) in the interconnection layer (comprising second metallization unit 618 and metal layer M5, Illustrative Fig. 4),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 4) and the second vertical structure (second vertical structure, Illustrative Fig. 4) vertically connect the logic cell region (logic cell region, Illustrative Fig. 4) and the large metal layer (metal layer 8, Illustrative Fig. 4),
wherein the first vertical structure (first vertical structure, Illustrative Fig. 4) is configured to provide a first current path (first current path, Illustrative Fig. 4) and a second current path (first current path, Illustrative Fig. 4) which vertically extend from the logic cell region (logic cell region, Illustrative Fig. 4), and
n is an integer from 9 to 15 (Ou does not explicitly disclose that n is an integer from 9 to
15. However, Ou teaches that a greater number of layers can be used in the vertical structures, without actually specifying the numbers of layers ([0034]), as also evidenced by Hou (US 2014/0306341 A1) and Peng (US 2021/0343650 A1), who are also teaching multilayer interconnect structures for logic devices. While Peng shows an interconnect structure with 11 metal layers (within the range of claimed invention) in an embodiment (Fig. 2A, [0070]), Hou discloses that number of metal layers (M1 to Mn, Fig. 2B) in the vertical structure (interconnecting structure 30, Fig. 2B) may be any number ([0037]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the number of metal layers in the vertical structures can be a design choice and determined according to optimization of the manufacturing cost, space requirements and device performance.)
Ou, however, does not teach that
the second vertical structure is configured to provide a third current path and a fourth current path which vertically extend from the logic cell region,
the first current path and the second current path are merged in an interconnection line of an (n-2)-th metal layer, forming a first merged current path connected to the largest metal layer,
the third current path and the fourth current path are merged in an interconnection line of the n-th metal layer, forming a second merged current path connected to the largest metal layer.
Ku, on the other hand, provides a motivation to modify Ou to make the second vertical structure identical the second vertical structure of the current application, to use the vertical structures in a driver/receiver device (Fig. 4, col.5, lines 50-54). Therefore, the combination of Ou and Ku further teaches that
the second vertical structure is configured to provide a third current path and a fourth current path which vertically extend from the logic cell region.
No prior art has been identified to modify the semiconductor device of Ou further to obtain the limitations “the first current path and the second current path are merged in the lower interconnection line of the uppermost unit structure of the plurality of unit structures, forming a first merged current path connected to the large metal layer” and “the third current path and the fourth current path are merged in the connection line, forming a second merged current path connected to the large metal layer“. Therefore, claim 16 is allowed.
Claims 17-20 are also allowed, because claims 17-20 inherit the allowable subject matter directly or indirectly from claim 16.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 3-5, 11, and 14 per response dated 5/5/2026. Applicant's arguments with respect to claims have been fully considered.
Applicant’s amendments to independent claims 1 and 11 overcame their corresponding 35. U.S.C. 102 rejections based on Tolpygo (Tolpygo et al., 2014, Supercond. Sci. Technol. 27 025016, DOI 10.1088/0953-2048/27/2/025016) set forth in the final office action which was mailed on 3/6/2026. Claim 1, however, is now rejected under new grounds based on a new prior art, Ku (US 9,977,857 B1). For claim 11, however, no grounds for rejection have been found, and claims 11-15 are now indicated as allowable.
Regarding the claims that depend on claim 1, claims 2-3 and 5-10 are also rejected. Even though claim 5 was indicated as allowable in the final office action, now after amendments made to independent claim 1 and claim 5, claim 5 now includes subject matter which is not disclosed in the Specification or Figures. This issue was discussed with the Applicant (Christian LaPense) during a phone call (see attached interview summary), and accordingly, claim 5 is now also rejected under 35 U.S.C. 112(a). There have been no grounds for rejection found for claim 4, which remained objected as in the final office action. On the other hand, claim 6, which was objected in the final office action is now rejected after applying the new prior art Ku to claim 1.
For the purpose of compact prosecution, the Examiner notes that incorporating limitations from objected claim 4 into claim 1 or clarifying the spatial arrangement of upper interconnection lines further might render claim 1 to overcome the current rejection.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ku (US 2020/0004917 A1) teaches a semiconductor device with an interconnection layer similar to one in the current application and is relevant to all claims.
Lee (US 2018/0294226 A1) teaches a semiconductor device with an interconnection layer similar to the one in the current application and is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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